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參數(shù)資料
| 型號： | AX88780 |
| 廠商： | ASIX Electronics Corporation |
| 英文描述： | High-Performance Non-PCI Single-Chip 32-bit 10/100M Fast Ethernet Controller |
| 中文描述： | 高性能非PCI單芯片32位10/100M自適應快速以太網(wǎng)控制器 |
| 文件頁數(shù)： | 23/49頁 |
| 文件大?。?/td> | 687K |
| 代理商： | AX88780 |
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AX88780
4.14 RXBOUND--RX Boundary Pointer Register
Offset Address = FC38h Default = 32’h0000_07FF
Field
Name
Type
Default
31:11
-
R
All 0’s
10:0
RXBUNPTR
R/W
All 0’s
Description
Reserved
RX Line Boundary Pointer.
Point to the last line that has been read by driver. The unit of line is 16
bytes.
When driver finished reading packet from RX buffer, it must update this
field.
4.15 MAC_CFG0--MAC Configuration0 Register
Offset Address = FC40h Default = 32’h0000_9157
Field
Name
Type
Default
31:16
-
R
All 0’s
15
SPEED100
R/W
1
Description
Reserved
Line Speed Mode
When this bit is enabled, The MAC of AX88780 will operate in 100M
speed, otherwise it will operate in 10M speed. The line speed must
co-operate with setting of PHY.
1 = 100M
0 = 10M
Reserved,
this bit must set to 0 for normal operation
Reserved, this bit must set to 0 for normal operation.
TX Flow Control
If this bit is enabled, MAC will perform TX flow control and send pause
on/off frame when receive buffer become low water level.
1 = enable
0 = disable
Reserved, this bit must set to 0 for normal operation.
Inter Packet Gap time: (IPG)
This field defines the back-to-back transmit packet gap for 10.100M only.
Reserved, keep the default value for normal operation.
14
13
12
-
-
R/W
R/W
R/W
0
0
1
TXFLOW_EN
11
10:4
-
R/W 0
R/W
IPGT
7’h15
3:0
-
R/W
4’h7
4.16 MAC_CFG1--MAC Configuration1 Register
Offset Address = FC44h Default = 32’h0000_6000
Field
Name
Type
Default
31:15
-
R
All 0’s
14
PUSRULE
R/W
1
Description
Reserved
Pause Frame Check Rule
When this bit is set, AX88780 accepts pause frame that DA can be any
value.
1 = don’t check DA field.
0 = check DA is equal to “01 80 C2 00 00 01”
Check CRC of received Packet.
When this bit is enabled, AX88780 will drop any CRC error packet.
1 = enable
0 = disable
Reserved, keep all bits in ‘0’ for normal operation.
Duplex Mode.
13
CRCCHK
R/W
1
12:7
6
-
R/W
R/W 0
All 0’s
DUPLEX
23
ASIX ELECTRONICS CORPORATION
相關PDF資料 |
PDF描述 |
|---|---|
| AX88790L | 10/100BASE 3-in-1 PCMCIA Fast Ethernet Controller |
| AX88796BLF | IC,MC14411P |
| AX88796BLI | Low-pin-count Non-PCI 8/16-bit 10/100M Fast Ethernet Controller |
| AX88872P | 10/100BASE Dual Speed “Swipeater” Controller |
| AX9902MS | 2N and 2P-Channel Enhancement Mode Power MOSFET |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AX88780_07 | 制造商:ASIX 制造商全稱:ASIX 功能描述:High-Performance Non-PCI Single-Chip 32-bit 10/100M Fast Ethernet Controller |
| AX88782 | 制造商:ASIX 制造商全稱:ASIX 功能描述:ASIX Multi-Port Ethernet Controller |
| AX88783 | 制造商:ASIX 制造商全稱:ASIX 功能描述:ASIX Multi-Port Ethernet Controller |
| AX88790L | 制造商:ASIX 制造商全稱:ASIX 功能描述:10/100BASE 3-in-1 PCMCIA Fast Ethernet Controller |
| AX88796 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:3-in-1 Local Bus Fast Ethernet Controller |
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