參數(shù)資料
型號(hào)： AX88780
廠商： ASIX Electronics Corporation
英文描述： High-Performance Non-PCI Single-Chip 32-bit 10/100M Fast Ethernet Controller
中文描述： 高性能非PCI單芯片32位10/100M自適應(yīng)快速以太網(wǎng)控制器
文件頁(yè)數(shù)： 10/49頁(yè)
文件大小： 687K
代理商： AX88780
AX88780
2.4 Regulator Interface
Table 3 : Regulator signals group
Pin Name Type
VCC33R
GNDR
REG_EN
V25OUT
Pin No.
37
36
39
38
Pin Description
VCC3R
GNDR
I3
O2
3.3V power to internal regulator
Ground pin for internal regulator
High to enable internal regulator. Low to disable internal regulator.
2.5V output from internal regulator, max 250mA, when REG_EN pin is high.
2.5 10/100M PHY Interface
Table 4 : 10/100M Twisted-pair signals group
Pin No.
83
Differential received input signal for both 10BASE-T and 100BSE-TX modes.
84
Differential received input signal for both 10BASE-T and 100BSE-TX modes.
93
Differential transmitted output signal for both 10BASE-T and 100BASE-TX modes.
94
Differential transmitted output signal for both 10BASE-T and 100BASE-TX modes
Pin Name
RXIN
RXIP
TXON
TXOP
Type
I
I
O
O
Pin Description
2.6 MII Interface (optional)
Table 5 : MII Interface signals group
Pin Name Type
TXEN
Pin No.
66
Pin Description
O2, 12mA
Transmit Enable:
TXEN is transition synchronously with respect to the rising edge of TXCLK. TXEN
indicates that the port is presenting nibbles on TXD [3:0] for transmission.
Transmit Data:
TXD[3:0] is transition synchronously with respect to the rising edge of TXCLK.
Transmit Clock:
TXCLK is a continuous clock from PHY. It provides the timing reference for the
transfer of the TXEN and TXD[3:0] signals from the MII port of PHY.
Receive Clock:
RXCLK is a continuous clock that provides the timing reference for the transfer of the
RXDV, RXD[3:0].
Receive Data:
RXD[3:0] is driven by the PHY synchronously with respect to RXCLK.
Receive Data Valid:
RXDV is driven by the PHY synchronously with respect to RXCLK. Asserted high
when valid data is present on RXD [3:0].
Collision signal:
This signal is driven by PHY when collision is detected.
Carrier Sense:
Asynchronous signal CRS is asserted by the PHY when either the transmit or receive
medium is non-idle.
Station Management Data Input /Output:
Serial data input/Output transfers from/to the PHY. The transfer protocol conforms to
the IEEE 802.3u MII specification.
Station Management Data Clock:
The timing reference for MDIO. All data transfers on MDIO are synchronized to the
rising edge of this clock.
An interrupt signal from PHY, active low.
TXD[3:0]
O2, 12mA
61,62,
63,65
69
TXCLK
I2
RXCLK
I2
71
RXD[3:0]
I2
74,75,
76,77
70
RXDV
I2
COL
I2
80
CRS
I2
79
MDIO
IO3,
8mA,PU
59
MDC
O3, 8mA
58
PHYINTN I2
46
10
ASIX ELECTRONICS CORPORATION
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