參數(shù)資料
型號: AX88780
廠商: ASIX Electronics Corporation
英文描述: High-Performance Non-PCI Single-Chip 32-bit 10/100M Fast Ethernet Controller
中文描述: 高性能非PCI單芯片32位10/100M自適應(yīng)快速以太網(wǎng)控制器
文件頁數(shù): 20/49頁
文件大?。?/td> 687K
代理商: AX88780
AX88780
01: Descriptor 1 in transmitting
10: Descriptor 2 in transmitting
11: Descriptor 3 in transmitting
TX Descriptor3 Occupied
Driver set this bit to ‘1’ to indicate that it had used TX descriptor3. When the
transmission is finished, AX88780 will auto-clear this bit.
TX Descriptor2 Occupied
Driver set this bit to ‘1’ to indicate that it had used TX descriptor2. When the
transmission is finished, AX88780 will auto-clear this bit.
TX Descriptor1 Occupied
Driver set this bit to ‘1’ to indicate that it had used TX descriptor1. When the
transmission is finished, AX88780 will auto-clear this bit.
TX Descriptor0 Occupied
Driver set this bit to ‘1’ to indicate that it had used TX descriptor0. When the
transmission is finished, AX88780 will auto-clear this bit.
3
TXD3O
R/W
0
2
TXD2O
R/W
0
1
TXD1O
R/W
0
0
TXD0O
R/W
0
4.7 PHY_CTRL-- Internal PHY Control Register
Offset Address = FC1Ch Default = 32’h0000_0000
Field
Name
Type
31:13
-
R
12
SPD_GPIO1
R/W
Default
All 0’s
0
Description
Reserved
Speed LED or GPIO1
When this bit is enabled, pin54 is as speed indicator, otherwise it is as
GPIO1 function and controlled by GPIO_CTRL register.
1= enable
0= disable
Link LED or GPIO0
When this bit is enabled, pin55 is as link/traffic indicator, otherwise it is
as GPIO0 function and controlled by GPIO_CTRL register.
1 = enable
0 = disable
EECS Pin as Full-Duplex LED
When this bit is enabled, EECS pin will be as full-duplex indicator and
EEDI pin will be as collision indicator.
1 = enable
0 = disable
Power down PHY
When this bit is enabled, AX88780 will power down internal PHY.
1 = enable
0 = disable
PHY Selection
When this bit is enabled, AX88780 will select internal PHY, otherwise it
will select external PHY.
1 = enable
0 = disable
Reserved
Internal 10/100M PHY operation mode
Driver can set these bits to control internal PHY operation mode.
3’b000 = auto-negotiation enable with all capability
3’b001 = auto-negotiation with 100BASE-TX FDX/HDX ability
3’b010 = auto-negotiation with 10BASE-T FDX/HDX ability
3’b011 = Reserved
3’b100 = Manual selection of 100BASE-TX FDX
3’b101 = Manual selection of 100BASE-TX HDX
3’b110 = Manual selection of 10BASE-T FDX
3’b111 = Manual selection of 10BASE-T HDX
11
LNK_GPIO0
R/W
0
10
FUL_EECS
R/W
0
9
PWDN
R/W
0
8
PHY_EN
R/W
0
7
6:4
-
R
R/W
0
3’b000
PHYOPMODE
20
ASIX ELECTRONICS CORPORATION
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