參數(shù)資料
型號(hào): AX88780
廠商: ASIX Electronics Corporation
英文描述: High-Performance Non-PCI Single-Chip 32-bit 10/100M Fast Ethernet Controller
中文描述: 高性能非PCI單芯片32位10/100M自適應(yīng)快速以太網(wǎng)控制器
文件頁數(shù): 19/49頁
文件大小: 687K
代理商: AX88780
AX88780
4.4 TX_CFG--TX Configuration Register
Offset Address = FC10h Default = 32’h0000_0040
Field Name
Type
Default
31:7
-
R
All 0’s
6
TXCRCAP
R/W
1
Description
Reserved
TXCRC Auto-Append
When this bit is enabled, AX88780 will append CRC to the transmitted
packet in FCS field.
1 = enable
0 = disable
Reserved.
TX Checksum Generation
When this bit is enabled, AX88780 will append checksum to the transmitted
packet that is IP or TCP or UDP packet.
1 = enable
0 = disable
Reserved
TX Description Status
AX88780 reports which descriptor is transmitted now
Default: 2’b00
5
4
-
R/W
R/W
0
0
TXCHKSUM
3:2
1:0
-
R
R
2’b00
2’b00
TXDS
4.5 TX_CMD--TX Command Register
Offset Address = FC14h Default = 32’h0000_0000
Field
Name
Type
Default
31:16
-
R
All 0’s
15
HWI
R/W
0
Description
Reserved
Host Writes Indication
Before host begins to send a packet to TX buffer, this bit should be set. At
the end of host writes the packet, this bit should be cleared.
1 = Start Writing
0 = End Writing
TX Descriptor Pointer
To specify which TX descriptor to be written.
Reserved
Byte Count.
Data length is written to transmitted buffer.
14:13
TXDP
R/W
2’b00
12
11:0
-
R/W
R/W
0
All 0’s
DATALEN
4.6 TXBS--TX Buffer Status Register
Offset Address = FC18h Default = 32’h0000_0000
Field Name
Type
Default Description
31:4
-
R
All 0’s
8
INTXDS
R
0
Reserved
Internal TX descriptor status.
This bit reports the TX descriptor status. When there are data not to be
transmitted, this bit will be set to ‘1’ otherwise it will be ‘0’
1 = have data in TX buffer
0 = all data are transmitted to cable
Reserved
TX Descriptor In Transmitting
These status bits indicate which descriptor is transmitting now.
00: Descriptor 0 in transmitting
7:6
5:4
-
R
2’b00
2’b00
TXDUSE R
19
ASIX ELECTRONICS CORPORATION
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