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| 型號： | AU1500PCIPERF_30275A |
| 英文描述： | AMD Alchemy? SolutionsAu1500? Processor PCI Bus Performance? 330KB (PDF) |
| 中文描述： | 采用AMD Alchemy？ SolutionsAu1500？ PCI總線處理器的性能？ 330KB（PDF格式） |
| 文件頁數(shù)： | 7/18頁 |
| 文件大?。?/td> | 128K |
| 代理商： | AU1500PCIPERF_30275A |
Application Note
7
PCI Bus Software Support for the Au1500
Rev. 1.3
August 2002
On the Au1500, GPIO200 defaults to an output that drives low (a zero). This pin is intended to drive
the PCI bus RST# signal. If the board-design utilizes GPIO200 in this capacity, then software must
drive GPIO200 according to the PCI bus reset timing. The following code snippet de-asserts RST# by
driving GPIO200 high (no need to drive it low since it defaults to low).
li t0, 0xB1700000 /* base address of GPIO2 */
li t1, 3 /* gpio2_enable[MR=1,CE=1]
sw t1, 0x0010(t0) /* gpio2_enable, provide clocks */
li t1, 1 /* gpio2_enable[MR=0,CE=1]
sw t1, 0x0010(t0) /* gpio2_enable, take away reset */
li t1, 1 /* gpio2_dir[GPIO200=1], output
sw t1, 0x0000(t0) /* gpio2_dir, set GPIO200 as output */
li t1, 0x00010001 /* gpio2_output[GPIO200ENA=1,GPIO200=1] */
sw t1, 0x0008(t0) /* gpio2_output, GPIO200 = 1 */
Note:
NOTE: If GPIO200 (or other GPIO) is not used to control PCI RST#, then PCI RST# must
also be tied to the Au1500 RSTIN signal. See the Au1500 Specification Update for additional
information.
5.3
Configure the PCI Controller
The PCI controller contains configuration registers which are located at physical address 0x0
14005000 (KSEG1 address 0xB4005000). A simple host bridge setup is provided in Table 2 on
page 7.
Table 2.
Host Bridge Configuration
Register
KSEG1
Address
Value
pci_cmem
0xB4005000
0x00000000
pci_config
0xB4005004
0x0000000F
pci_b2bmask_cch
0xB4005008
0x00000000
pci_b2bbase0_venid
0xB400500C
0x00000000
pci_b2bbase1_id
0xB4005010
0x00000000
pci_mwmask_dev
0xB4005014
0xE0000000
pci_mwbase_rev_ccl
0xB4005018
0x00000000
pci_err_addr
0xB400501C
-
pci_spec_intack
0xB4005020
-
pci_id
0xB4005100
0x00001755
pci_statcmd
0xB4005104
0x02A00356
pci_classrev
0xB4005108
0x00000000
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