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| 型號(hào)： | AU1500PCIPERF_30275A |
| 英文描述： | AMD Alchemy? SolutionsAu1500? Processor PCI Bus Performance? 330KB (PDF) |
| 中文描述： | 采用AMD Alchemy？ SolutionsAu1500？ PCI總線處理器的性能？ 330KB（PDF格式） |
| 文件頁數(shù)： | 6/18頁 |
| 文件大小： | 128K |
| 代理商： | AU1500PCIPERF_30275A |
6
Application Note
Rev. 1.3
August 2002
PCI Bus Software Support for the Au1500
is more challenging, but in most cases can be easily solved with the use of static or “wired” TLB
entries to directly map regions on the PCI bus of interest to the RTOS.
Most other operating systems or applications without operating systems can use one or more of the
techniques described herein.
NOTE: This document assumes a little-endian core configuration. Since PCI is inherently little-
endian, with both the Au1 core and PCI in little-endian, each has the same “view” of memory.
Utilizing the Au1 core in big-endian mode is possible, and the issues are discussed in “Big-Endian
Considerations” on page 17.
5. Au1500 PCI Host Bridge Configuration
The Au1500 integrated PCI controller must be configured before it is utilized. This document
assumes configuration of a host bridge (via the PCI_CFG pin). The steps necessary to configure the
controller are as follows.
1.
Enable the PCI bus 33 and/or 66 MHz clock source.
2.
Take the Au1500 PCI controller and PCI bus out of reset.
3.
Configure the Au1500 PCI controller registers.
The PCI controller requires these steps, in order, to ensure proper operation.
5.1
Enable PCI Bus Clock
The 33 or 66 MHz PCI clock can be generated either internally or externally, depending upon the
application/board-design. For issues pertaining to PCI clock generation, see the “PCI Clock
Generation” applications note.
If the PCI clock is generated internally, the clock generator registers must be programmed to generate
the PCI clock.
If the PCI clock is generated externally, it must be enabled and running.
5.2
Enable PCI controller
The PCI bus signal RST# must be asserted for at least 100 microseconds after the PCI clock has
stablized. It then must be negated for a minimum of 5 PCI clocks before accessing the PCI bus.
Additional reset timing parameters are in the PCI 2.2. specification:
“4.2.3.2. Timing Parameters”
and “4.3.2. Reset”.
The PCI bus RST# signal also resets the Au1500 PCI controller. As such, RST# must be driven low
and then high according to the PCI reset timing to reset both the PCI bus and the Au1500 integrated
PCI controller. The Au1500 PCI controller must be taken out of reset and 5 PCI clocks elapsed
before
any of its configuration registers can be accessed.
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