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| 型號(hào)： | AU1500PCIPERF_30275A |
| 英文描述： | AMD Alchemy? SolutionsAu1500? Processor PCI Bus Performance? 330KB (PDF) |
| 中文描述： | 采用AMD Alchemy？ SolutionsAu1500？ PCI總線處理器的性能？ 330KB（PDF格式） |
| 文件頁數(shù)： | 11/18頁 |
| 文件大?。?/td> | 128K |
| 代理商： | AU1500PCIPERF_30275A |
Application Note
11
PCI Bus Software Support for the Au1500
Rev. 1.3
August 2002
6.2
Type 1 Configuration Cycles
Type 1 configuration cycles are used to configure PCI devices on a remote PCI bus. The address
phase of a Type 1 configuration cycle is the following:
Figure 4: Type 1 Configuration Cycle
Bit 31 of the 36-bit physical address is a one and causes the PCI controller to emit “01” on
PCI_AD[1:0]. Bits [30:2] of the 36-bit physical address are copied directly to bits AD[30:2]. The
following table illustrates the 36-bit physical addresses for Type 1 configuration space addresses.
In the table above, “df” represents the device number and function number which form
PCI_AD[15:8], and “bb” represents the bus number which forms PCI_AD[23:16].
6.3
Auto-Configuration Considerations
At boot and/or run-time, PCI auto-configuration software scans the PCI configuration space in search
of PCI devices. When a device is detected, the device is allocated PCI memory and/or I/O space and
its MBAR(s) are programmed with a unique base address. When completed, the PCI bus scan creates
a conflict-free address map for the PCI bus.
7
PCI_AD[18]
0x6 00040000
17
PCI_AD[28]
0x6 10000000
8
PCI_AD[19]
0x6 00080000
18
PCI_AD[29]
0x6 20000000
9
PCI_AD[20]
0x6 00100000
19
PCI_AD[30]
0x6 40000000
Table 5.
Au1500 Type 1 Configuration Cycle Base Addresses
Bus
36-Bit Physical
Address
Bus
36-Bit Physical
Address
0
0x6 8000df00
4
0x6 8004df00
1
0x6 8001df00
5
0x6 8005df00
2
0x6 8002df00
255
0x6 80FFdf00
3
0x6 8003df00
bb (<= 255)
0x6 80bbdf00
Table 4.
Au1500 Type 0 Configuration Cycle Base Addresses (Continued)
Device
Number
IDSEL
36-Bit Physical
Address
Device
Number
IDSEL
36-Bit Physical
Address
31 30
11 10
8 7
2 1
0
Reserved
Function
Register
01
Bus
Device
PCI_AD[31:0]
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