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| 型號(hào)： | AU1500PCIPERF_30275A |
| 英文描述： | AMD Alchemy? SolutionsAu1500? Processor PCI Bus Performance? 330KB (PDF) |
| 中文描述： | 采用AMD Alchemy？ SolutionsAu1500？ PCI總線處理器的性能？ 330KB（PDF格式） |
| 文件頁數(shù)： | 16/18頁 |
| 文件大?。?/td> | 128K |
| 代理商： | AU1500PCIPERF_30275A |
16
Application Note
Rev. 1.3
August 2002
PCI Bus Software Support for the Au1500
The address and mask values for pci_cmem are application-specific; there is no general-purpose
setting for pci_cmem. As such, the need for this performance feature must be determined by the
application designer.
A graphics video frame buffer would benefit from the cache-able PCI memory window. Note that that
the PCI auto-configuration software must allocate the frame buffer MBAR in an address covered by
pci_cmem. This may require more careful planning of the PCI memory space address map.
7.3
Fast Back-To-Back Accesses
The Au1500 PCI controller supports fast back-to-back accesses. If the 36-bit physical from the TLB
hits in the Au1500 PCI controller fast back-to-back range (as determined by pci_b2bmask,
pci_b2bbase0 and pci_b2bbase1), then the Au1500 controller will use fast back-to-back signalling.
7.4
Direct Memory Access, DMA
PCI devices can perform direct memory accesses, DMA, into Au1500 memory. For PCI device DMA
into Au1500 memory, the Au1500 memory window must be enabled, see “Au1500 Memory
Window” on page 8.
PCI devices that perform DMA are PCI bus masters. The Au1500 internal PCI bus arbiter can be used
to grant different PCI bus masters (up to 4) the bus, or an external arbiter can be used. The decision is
application specific, and the choice of arbiter must be reflected in the pci_config[AEN] bit.
The device drivers for PCI devices should utilize the bus address translation routines previously
described in “Memory Window Considerations” on page 8. DMA engines need PCI space address
pointers, and software needs virtual address pointers. The bus address translation routines are used to
convert pointers from PCI address space to MIPS virtual address space.
7.5
Miscellaneous
All PCI memory accesses are first translated by the TLB into a PCI physical address. Since the TLB
is of finite size (32 entries), it is possible that TLB faults will occur while accessing PCI memory
space. Performance to PCI memory space improve by utilizing static, or wired, TLB entries. With
static TLB entries, TLB faults are eliminated so as to remove the overhead involved in a TLB fault.
Of course, the number of static TLB entries to use and which PCI spaces to cover are application
specific.
8. PCI I/O Space
All PCI accesses first travel through the Au1500 TLB to yield a 36-bit physical address. PCI I/O
space accesses are designated by the TLB producing the 36-bit physical address 0x5 xxxxxxxx. On a
read to PCI I/O space, the Au1 core stalls waiting for data, and on a write, the data flows through the
write-buffer, stalling only if the write-buffer is full.
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