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| 型號(hào)： | AU1500PCIPERF_30275A |
| 英文描述： | AMD Alchemy? SolutionsAu1500? Processor PCI Bus Performance? 330KB (PDF) |
| 中文描述： | 采用AMD Alchemy？ SolutionsAu1500？ PCI總線(xiàn)處理器的性能？ 330KB（PDF格式） |
| 文件頁(yè)數(shù)： | 13/18頁(yè) |
| 文件大?。?/td> | 128K |
| 代理商： | AU1500PCIPERF_30275A |
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Application Note
13
PCI Bus Software Support for the Au1500
Rev. 1.3
August 2002
6.4
Software Techniques
Most operating systems have a PCI configuration space support application programming interface,
API, similar to the following: [4]
uint8
pciCfgRd8 (bus, device, func, reg);
uint16 pciCfgRd16 (bus, device, func, reg);
uint32 pciCfgRd32 (bus, device, func, reg);
void
pciCfgWr8 (bus, device, func, reg, data);
void
pciCfgWr16 (bus, device, func, reg, data);
void
pciCfgWr32 (bus, device, func, reg, data);
For Type 0 configuration cycles, the lower 32-bits of the 36-bit physical address are computed in this
fashion:
addr = ((1 << device) << 11) | (func << 8)| reg;
For Type 1 configuration cycles, the lower 32-bits of the 36-bit physical address are computed in this
fashion:
addr = (1 << 31) | (bus << 16) | (device << 11) | (func << 8) | reg;
With the lower 32-bits of the physical address computed, it is necessary to create a valid TLB entry in
order to obtain a mapping onto the PCI configuration space.
There are three primary approaches for mapping PCI configuration space and performing PCI
configuration cycles:
Technique #1) Allocate a fixed TLB entry, and dynamically map/unmap the TLB to the computed 36-
bit PCI configuration cycle address, or
Technique #2) Allocate a fixed TLB entry which covers most of the configuration space, or
Technique #3) Dynamically map/unmap the 36-bit PCI configuration address from the current
process address space.
6.4.1
Configuration Space Access Technique #1
Technique #1 is for operating systems (e.g. Linux, RTOSes, or other operating environments), in
which device drivers do NOT have their own unique address space, and therefore can not
dynamically map/unmap PCI configuration space on demand.
A TLB entry (e.g. TLB index 0) must be allocated for the specific purpose of PCI configuration
cycles. The MIPS CP0 register Wired (i.e. CP0 register 6) must be adjusted accordingly to prevent
random TLB updates from over-writing the entry allocated to the PCI configuration space. The
PageMask should be set to 4KB.
Furthermore, a TLB-translated address range (KUSEG, KSEG2 or KSEG3) must be reserved for the
purpose of providing a 4KB window into PCI configuration space. This 4KB window is sufficient to
cover a PCI Configuration header and is the single window for
all
PCI configuration accesses.
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