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10
Application Note
Rev. 1.3
August 2002
PCI Bus Software Support for the Au1500
6. PCI Configuration Cycles
PCI configuration cycles are used to configure devices that are attached to the PCI bus. The
configuration space is normally scanned by software to identify and more importantly configure the
devices for proper behavior on the PCI bus.
The PCI configuration space address is derived from the Au1 36-bit physical address: bits [35:32]=6
indicate PCI configuration space, bit [31] indicates a Type 0 or Type 1 configuration cycle, and bits
[30:2] are copied directly to the PCI_AD[30:2].
Note:
NOTE: The Au1500 PCI controller does not respond to a configuration cycle from itself. As
such it will not be detected by a PCI bus scan.
6.1
Type 0 Configuration Cycles
Type 0 configuration cycles are the most common. The address phase of a Type 0 configuration cycle
is the following:
Figure 3: Type 0 Configuration Cycle
Bit 31 of the 36-bit physical address is a zero and causes the PCI controller to emit “00” on
PCI_AD[1:0]. During the address phase, only one bit is permitted to be set in the Device number
field. The single “1” bit denotes the IDSEL of a PCI target device for the configuration cycle. A total
of 20 target devices is supported. The following table enumerates the 20 possible configuration
spaces.
Table 4.
Au1500 Type 0 Configuration Cycle Base Addresses
Device
Number
IDSEL
36-Bit Physical
Address
Device
Number
IDSEL
36-Bit Physical
Address
0
PCI_AD[11]
0x6 00000800
10
PCI_AD[21]
0x6 00200000
1
PCI_AD[12]
0x6 00001000
11
PCI_AD[22]
0x6 00400000
2
PCI_AD[13]
0x6 00002000
12
PCI_AD[23]
0x6 00800000
3
PCI_AD[14]
0x6 00004000
13
PCI_AD[24]
0x6 01000000
4
PCI_AD[15]
0x6 00008000
14
PCI_AD[25]
0x6 02000000
5
PCI_AD[16]
0x6 00010000
15
PCI_AD[26]
0x6 04000000
6
PCI_AD[17]
0x6 00020000
16
PCI_AD[27]
0x6 08000000
31
11 10
8 7
2 1
0
Device
Function
Register
00
PCI_AD[31:0]