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| 型號(hào)： | AU1500PCIPERF_30275A |
| 英文描述： | AMD Alchemy? SolutionsAu1500? Processor PCI Bus Performance? 330KB (PDF) |
| 中文描述： | 采用AMD Alchemy？ SolutionsAu1500？ PCI總線處理器的性能？ 330KB（PDF格式） |
| 文件頁(yè)數(shù)： | 17/18頁(yè) |
| 文件大?。?/td> | 128K |
| 代理商： | AU1500PCIPERF_30275A |
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Application Note
17
PCI Bus Software Support for the Au1500
Rev. 1.3
August 2002
PCI I/O space accesses may only be non-cache-able, and therefore must utilize CCA encoding 2.
A static, or wired, TLB entry may be desirable to reduce the possibility of TLB faults and the
overhead associated with handling a TLB fault. The number of static TLB entries to use is application
specific.
9. PCI Interrupts
TBD
10. Big-Endian Considerations
TBD
11. Satellite Mode
The Au1500 PCI controller is configured for satellite mode when the pin PCI_CFG is zero. The use
of a satellite-mode Au1500 is very much application-specific; however, there are a few guidelines to
follow.
The PCI configuration registers at 0xB40051xx are
not
visible to the processor.
When in satellite mode, the registers at KSEG1 address 0xB40051XX are not visible to the Au1 core.
As such, these registers must not be accessed during initialization of the PCI controller.
The PCI configuration registers must be configured before clearing the pci_config[PD] bit.
The pci_config[PD] prevents the Au1500 PCI controller from responding to accesses. The Au1500
PCI configuration registers must be programmed with the appropriate values, then pci_config[PD] bit
cleared. By default, this bit is set so that the controller does not respond to PCI accesses until the PCI
controller is configured.
The Au1500 responds to configuration cycles.
When in satellite mode, the Au1500 PCI controller does respond to configuration cycles. As such, it
does appear during a normal PCI bus scan. (In host mode, the Au1500 PCI controller does not
respond to configuration cycles.)
The Au1500 memory window size (pci_mwmask) is reflected in the MBAR during a configuration
cycle access.
During a PCI bus scan, the auto-configuration software manipulates the MBAR to determine the size
of the memory window. The size programmed via pci_mwmask is reflected in the MBAR during the
PCI bus scan so that the proper size is reported to the auto-configuration software.
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