參數(shù)資料
型號： ATTINY13V-10SUR
廠商： Atmel
文件頁數(shù)： 75/176頁
文件大?。?/td> 0K
描述： MCU AVR 1KB FLASH 10MHZ 8SOIC
產(chǎn)品培訓模塊： tinyAVR Introduction
標準包裝： 2,000
系列： AVR® ATtiny
核心處理器： AVR
芯體尺寸： 8-位
速度： 10MHz
外圍設備： 欠壓檢測/復位，POR，PWM，WDT
輸入/輸出數(shù)： 6
程序存儲器容量： 1KB（512 x 16）
程序存儲器類型： 閃存
EEPROM 大小： 64 x 8
RAM 容量： 64 x 8
電壓 - 電源 (Vcc/Vdd)： 1.8 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 4x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 8-SOIC（0.209"，5.30mm 寬）
包裝： 帶卷 (TR)
其它名稱： ATTINY13V-10SUR-ND
ATTINY13V-10SURTR
PIC16(L)F720/721
DS41430C-page 166
Preliminary
2010-2011 Microchip Technology Inc.
18.6
Protection Against Spurious Write
There are conditions when the device should not write
to the program memory. To protect against spurious
writes, various mechanisms have been built in. On
power-up, WREN is cleared. Also, the Power-up Timer
(64 ms duration) prevents program memory writes.
The write initiates sequence and the WREN bit helps
prevent an accidental write during brown-out, power
glitch or software malfunction.
18.7
Operation During Code-Protect
When the device is code-protected, the CPU is able to
read and write unscrambled data to the program
memory.
18.8
Operation During Write-Protect
When the program memory is write-protected, the CPU
can read and execute from the program memory.
The
portions
of
program
memory
that
are
write-protected can be modified by the CPU using the
PMCON registers, but the protected program memory
cannot be modified using ICSP mode.
REGISTER 18-1:
PMCON1: PROGRAM MEMORY CONTROL 1 REGISTER
U-1
R/W-0/0
R/W/HC-0/0
U-0
R/W-0/0
R/S/HC-0/0
—CFGS
LWLO
FREE
—WREN
WR
RD
bit 7
bit 0
Legend:
S = Setable bit, cleared in hardware
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
Unimplemented: Read as ‘1’
bit 6
CFGS: Flash Program/Configuration Select bit
1 = Accesses Configuration, user ID and device ID registers
0 = Accesses Flash program
bit 5
LWLO: Load Write Latches Only bit
1 =
The next WR command does not initiate a write to the PFM; only the program memory
latches are updated.
0 =
The next WR command writes a value from PMDATH:PMDATL into program memory latches
and initiates a write to the PFM of all the data stored in the program memory latches.
bit 4
FREE: Program Flash Erase Enable bit
1 =
Perform an program Flash erase operation on the next WR command (cleared by hardware
after completion of erase).
0 =
Perform a program Flash write operation on the next WR command
bit 3
Unimplemented: Read as ‘0’
bit 2
WREN: Program/Erase Enable bit
1 = Allows program/erase cycles
0 = Inhibits programming/erasing of Program Flash
bit 1
WR: Write Control bit
1 = Initiates a program Flash program/erase operation.
The operation is self-timed and the bit is cleared by hardware once operation is complete.
The WR bit can only be set (not cleared) in software.
0 = Program/erase operation to the Flash is complete and inactive
bit 0
RD: Read Control bit
1 = Initiates an program memory read (The RD is cleared in hardware; the RD bit can only be set
(not cleared) in software).
0 = Does not initiate a program memory read
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