參數(shù)資料
型號： ATTINY13V-10SUR
廠商： Atmel
文件頁數(shù)： 176/176頁
文件大小： 0K
描述： MCU AVR 1KB FLASH 10MHZ 8SOIC
產(chǎn)品培訓模塊： tinyAVR Introduction
標準包裝： 2,000
系列： AVR® ATtiny
核心處理器： AVR
芯體尺寸： 8-位
速度： 10MHz
外圍設備： 欠壓檢測/復位，POR，PWM，WDT
輸入/輸出數(shù)： 6
程序存儲器容量： 1KB（512 x 16）
程序存儲器類型： 閃存
EEPROM 大小： 64 x 8
RAM 容量： 64 x 8
電壓 - 電源 (Vcc/Vdd)： 1.8 V ~ 5.5 V
數(shù)據(jù)轉換器： A/D 4x10b
振蕩器型： 內部
工作溫度： -40°C ~ 85°C
封裝/外殼： 8-SOIC（0.209"，5.30mm 寬）
包裝： 帶卷 (TR)
其它名稱： ATTINY13V-10SUR-ND
ATTINY13V-10SURTR
2010-2011 Microchip Technology Inc.
Preliminary
DS41430C-page 99
PIC16(L)F720/721
13.5.3
TIMER1 GATE TOGGLE MODE
When Timer1 Gate Toggle mode is enabled, it is
possible to measure the full-cycle length of a Timer1
gate signal, as opposed to the duration of a single level
pulse.
The Timer1 gate source is routed through a flip-flop that
changes state on every incrementing edge of the sig-
nal. See Figure 13-4 for timing details.
Timer1 Gate Toggle mode is enabled by setting the
T1GTM bit of the T1GCON register. When the T1GTM
bit is cleared, the flip-flop is cleared and held clear. This
is necessary in order to control which edge is
measured.
13.5.4
TIMER1 GATE SINGLE-PULSE
MODE
When Timer1 Gate Single-Pulse mode is enabled, it is
possible to capture a single pulse gate event. Timer1
Gate Single-Pulse mode is first enabled by setting the
T1GSPM bit in the T1GCON register. Next, the
T1GGO/DONE bit in the T1GCON register must be set.
The Timer1 will be fully enabled on the next
incrementing edge. On the next trailing edge of the
pulse, the T1GGO/DONE bit will automatically be
cleared. No other gate events will be allowed to
increment Timer1 until the T1GGO/DONE bit is once
again set in software.
Clearing the T1GSPM bit of the T1GCON register will
also clear the T1GGO/DONE bit. See Figure 13-5 for
timing details.
Enabling the Toggle mode and the Single-Pulse mode
simultaneously will permit both sections to work
together. This allows the cycle times on the Timer1 gate
source to be measured. See Figure 13-6 for timing
details.
13.5.5
TIMER1 GATE VALUE STATUS
When Timer1 gate value status is utilized, it is possible
to read the most current level of the gate control value.
The value is stored in the T1GVAL bit in the T1GCON
register. The T1GVAL bit is valid even when the Timer1
gate is not enabled (TMR1GE bit is cleared).
13.5.6
TIMER1 GATE EVENT INTERRUPT
When Timer1 gate event interrupt is enabled, it is
possible to generate an interrupt upon the completion
of a gate event. When the falling edge of T1GVAL
occurs, the TMR1GIF flag bit in the PIR1 register will be
set. If the TMR1GIE bit in the PIE1 register is set, then
an interrupt will be recognized.
The TMR1GIF flag bit operates even when the Timer1
gate is not enabled (TMR1GE bit is cleared).
Note:
Enabling Toggle mode at the same time
as changing the gate polarity may result in
indeterminate operation.
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