參數(shù)資料
型號： ATTINY13V-10SUR
廠商： Atmel
文件頁數(shù)： 71/176頁
文件大小： 0K
描述： MCU AVR 1KB FLASH 10MHZ 8SOIC
產(chǎn)品培訓(xùn)模塊： tinyAVR Introduction
標準包裝： 2,000
系列： AVR® ATtiny
核心處理器： AVR
芯體尺寸： 8-位
速度： 10MHz
外圍設(shè)備： 欠壓檢測/復(fù)位，POR，PWM，WDT
輸入/輸出數(shù)： 6
程序存儲器容量： 1KB（512 x 16）
程序存儲器類型： 閃存
EEPROM 大?。?/td> 64 x 8
RAM 容量： 64 x 8
電壓 - 電源 (Vcc/Vdd)： 1.8 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 4x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 8-SOIC（0.209"，5.30mm 寬）
包裝： 帶卷 (TR)
其它名稱： ATTINY13V-10SUR-ND
ATTINY13V-10SURTR
PIC16(L)F720/721
DS41430C-page 162
Preliminary
2010-2011 Microchip Technology Inc.
FIGURE 18-1:
FLASH PROGRAM MEMORY READ CYCLE EXECUTION – NORMAL MODE
18.2
Code Protection
When the device is code-protected, the CPU may
continue to read and write the Flash program memory.
Depending on the settings of the Flash program
memory enable (WRT<1:0>) bits, the device may or
may not be able to write certain blocks of the program
memory. However, reads of the program memory are
allowed.
When the Flash program memory Code Protection
(CP) bit in the Configuration Word register is enabled,
the program memory is code-protected, and the device
programmer (ICSP) cannot access data or program
memory.
18.3
PMADRH and PMADRL Registers
The PMADRH:PMADRL register pair can address up
to a maximum of 4K words of program Flash. The Most
Significant Byte (MSB) of the address is written to the
PMADRH register and the Least Significant Byte (LSB)
is written to the PMADRL register.
18.4
PMCON1 and PMCON2 Registers
PMCON1 is the control register for the data program
memory accesses.
Control bits RD and WR initiate read and write,
respectively. These bits cannot be cleared, but only set
in software. They are cleared in hardware at the
completion of the read or write operation. The inability
to clear the WR bit in software prevents the accidental
premature termination of a write operation. Setting the
control bit WR initiates a write operation. For program
memory writes, WR initiates a write cycle if FREE = 0
and an erase cycle if FREE = 1.
The WREN bit, when set, will allow a write operation.
On power-up, the WREN bit is clear. PMCON2 is not a
physical register. Reading PMCON2 will read all ‘0’s.
The PMCON2 register is used exclusively in the Flash
memory write sequence.
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
BSF PMCON1, RD
Executed here
Forced NOP
Executed here
Forced NOP
Executed here
PC
PC + 1
PMADRH, PMADRL
PC+3
PC + 5
Flash ADDR
RD bit
INSTR (PC)
PMDATH, PMDATL
INSTR (PC + 3)
PC + 4
INSTR (PC + 4)
INSTR (PC + 1)
INSTR (PC - 1)
Executed here
INSTR (PC + 3)
Executed here
INSTR (PC + 4)
Executed here
Flash DATA
PMDATH
PMDATL
Register
Force
NOP
Stop
PC
Note:
Code-protect does not affect the CPU
from performing a read operation on the
program memory. For more information,
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