參數(shù)資料
型號: ATTINY13V-10SUR
廠商: Atmel
文件頁數(shù): 23/176頁
文件大?。?/td> 0K
描述: MCU AVR 1KB FLASH 10MHZ 8SOIC
產(chǎn)品培訓模塊: tinyAVR Introduction
標準包裝: 2,000
系列: AVR® ATtiny
核心處理器: AVR
芯體尺寸: 8-位
速度: 10MHz
外圍設(shè)備: 欠壓檢測/復位,POR,PWM,WDT
輸入/輸出數(shù): 6
程序存儲器容量: 1KB(512 x 16)
程序存儲器類型: 閃存
EEPROM 大?。?/td> 64 x 8
RAM 容量: 64 x 8
電壓 - 電源 (Vcc/Vdd): 1.8 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 4x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 8-SOIC(0.209",5.30mm 寬)
包裝: 帶卷 (TR)
其它名稱: ATTINY13V-10SUR-ND
ATTINY13V-10SURTR
2010-2011 Microchip Technology Inc.
Preliminary
DS41430C-page 119
PIC16(L)F720/721
16.0 ADDRESSABLE UNIVERSAL
SYNCHRONOUS
ASYNCHRONOUS RECEIVER
TRANSMITTER (AUSART)
The
Addressable
Universal
Synchronous
Asynchronous
Receiver
Transmitter
(AUSART)
module is a serial I/O communications peripheral. It
contains all the clock generators, shift registers and
data buffers necessary to perform an input or output
serial data transfer independent of device program
execution. The AUSART, also known as a Serial
Communications Interface (SCI), can be configured as
a full-duplex asynchronous system or half-duplex
synchronous system. Full-Duplex mode is useful for
communications with peripheral systems, such as CRT
terminals and personal computers. Half-Duplex
Synchronous mode is intended for communications
with peripheral devices, such as A/D or D/A integrated
circuits, serial EEPROMs or other microcontrollers.
These devices typically do not have internal clocks for
baud rate generation and require the external clock
signal provided by a master synchronous device.
The AUSART module includes the following capabilities:
Full-duplex asynchronous transmit and receive
Two-character input buffer
One-character output buffer
Programmable 8-bit or 9-bit character length
Address detection in 9-bit mode
Input buffer overrun error detection
Received character framing error detection
Half-duplex synchronous master
Half-duplex synchronous slave
Sleep operation
Block diagrams of the AUSART transmitter and
receiver are shown in Figure 16-1 and Figure 16-2.
FIGURE 16-1:
AUSART TRANSMIT BLOCK DIAGRAM
TXIF
TXIE
Interrupt
TXEN
TX9D
MSb
LSb
Data Bus
TXREG Register
Transmit Shift Register (TSR)
(8)
0
TX9
TRMT
SPEN
TX/CK
Pin Buffer
and Control
8
SPBRG
FOSC
÷ n
n
+ 1
Multiplier
x4
x16 x64
SYNC
100
BRGH
x10
Baud Rate Generator
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