參數(shù)資料
型號： ATTINY13V-10SUR
廠商： Atmel
文件頁數(shù)： 20/176頁
文件大?。?/td> 0K
描述： MCU AVR 1KB FLASH 10MHZ 8SOIC
產(chǎn)品培訓(xùn)模塊： tinyAVR Introduction
標(biāo)準(zhǔn)包裝： 2,000
系列： AVR® ATtiny
核心處理器： AVR
芯體尺寸： 8-位
速度： 10MHz
外圍設(shè)備： 欠壓檢測/復(fù)位，POR，PWM，WDT
輸入/輸出數(shù)： 6
程序存儲器容量： 1KB（512 x 16）
程序存儲器類型： 閃存
EEPROM 大?。?/td> 64 x 8
RAM 容量： 64 x 8
電壓 - 電源 (Vcc/Vdd)： 1.8 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 4x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 8-SOIC（0.209"，5.30mm 寬）
包裝： 帶卷 (TR)
其它名稱： ATTINY13V-10SUR-ND
ATTINY13V-10SURTR
PIC16(L)F720/721
DS41430C-page 116
Preliminary
2010-2011 Microchip Technology Inc.
15.3.4
PWM RESOLUTION
The resolution determines the number of available duty
cycles for a given period. For example, a 10-bit resolution
will result in 1024 discrete duty cycles, whereas an 8-bit
resolution will result in 256 discrete duty cycles.
The maximum PWM resolution is 10 bits when PR2 is
255. The resolution is a function of the PR2 register
value as shown by Equation 15-4.
EQUATION 15-4:
PWM RESOLUTION
15.3.5
OPERATION IN SLEEP MODE
In Sleep mode, the TMR2 register will not increment
and the state of the module will not change. If the CCP1
pin is driving a value, it will continue to drive that value.
When the device wakes up, TMR2 will continue from its
previous state.
15.3.6
CHANGES IN SYSTEM CLOCK
FREQUENCY
The PWM frequency is derived from the system clock
frequency (FOSC). Any changes in the system clock fre-
quency will result in changes to the PWM frequency.
additional details.
15.3.7
EFFECTS OF RESET
Any Reset will force all ports to Input mode and the
CCP registers to their Reset states.
15.3.8
SETUP FOR PWM OPERATION
The following steps should be taken when configuring
the CCP module for PWM operation:
1.
Disable the PWM pin (CCP1) output driver(s) by
setting the associated TRIS bit(s).
2.
Load the PR2 register with the PWM period value.
3.
Configure the CCP module for the PWM mode
by loading the CCP1CON register with the
appropriate values.
4.
Load the CCPR1L register and the DCxBx bits of
the CCP1CON register, with the PWM duty cycle
value.
5.
Configure and start Timer2:
Clear the TMR2IF interrupt flag bit of the PIR1
register. See Note below.
Configure the T2CKPS bits of the T2CON
register with the Timer2 prescale value.
Enable Timer2 by setting the TMR2ON bit of
the T2CON register.
6.
Enable PWM output pin:
Wait until Timer2 overflows, TMR2IF bit of the
PIR1 register is set. See Note below.
Enable the PWM pin (CCP1) output driver(s)
by clearing the associated TRIS bit(s).
Note:
If the pulse width value is greater than the
period the assigned PWM pin(s) will
remain unchanged.
Resolution
4PR2
1
+
log
2
log
------------------------------------------ bits
=
TABLE 15-4:
EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 20 MHz)
PWM Frequency
1.22 kHz
4.88 kHz
19.53 kHz
78.12 kHz
156.3 kHz
208.3 kHz
Timer Prescale (1, 4, 16)
16
4
1
PR2 Value
0xFF
0x3F
0x1F
0x17
Maximum Resolution (bits)
10
8
7
6.6
TABLE 15-5:
EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 8 MHz)
PWM Frequency
1.22 kHz
4.90 kHz
19.61 kHz
76.92 kHz
153.85 kHz
200.0 kHz
Timer Prescale (1, 4, 16)
16
4
1
PR2 Value
0x65
0x19
0x0C
0x09
Maximum Resolution (bits)
8
6
5
Note:
In order to send a complete duty cycle and
period on the first PWM output, the above
steps must be included in the setup
sequence. If it is not critical to start with a
complete PWM signal on the first output,
then step 6 may be ignored.
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