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參數(shù)資料
| 型號： | AT49BN1604 |
| 廠商： | Atmel Corp. |
| 英文描述： | 16-megabit Burst Mode 3-volt Only Flash Memory(16M位 3V猝發(fā)模式閃速存儲器) |
| 中文描述： | 16兆位突發(fā)模式3伏，只有閃存（1,600位3V的猝發(fā)模式閃速存儲器） |
| 文件頁數(shù)： | 3/19頁 |
| 文件大小： | 264K |
| 代理商： | AT49BN1604 |
AT49BN1604(T)
3
ing edge of the AVD signal whichever occurs first. The CLK
signal controls the flow of data from the device for a burst
operation. To perform a burst read, the BAA signal should
go low during the clock cycle prior to the beginning of the
burst. When the BAA signal is low, the data at the next
sequential address in memory is read for each following
clock cycle.
During a given burst mode read, any number of addresses
can be read from the memory. When a page boundary in
the memory is transitioned, additional time may be required
for the device to continue the burst read. To indicate that it
is not ready to continue the burst, the device will drive the
RDY pin low during the clock cycles in which new data is
not being presented. Once the RDY pin is driven high, the
next data will be valid. Starting with address zero, page
boundaries occur every 128 words in the memory. During
the burst mode, depending on the initial address that is
read, the first page boundary transition may occur before
128 words are read. The RDY signal will be tri-stated when
the CE or OE signal is high.
In the “Burst Read Cycle Waveform” as shown on page 13,
the data D0 is valid asynchronously from point A, the point
when the addresses are latched. The low to high transition
of the clock at point B results in no change of data because
the RDY signal is low. The low to high transition of the
clock at point C results in the first burst word, D1, being
read. The transition of the clock at point D results in a burst
read of the last word of the page, D127. The clock transi-
tion at point E does not cause new data to appear on the
output lines because the RDY signal goes low after the
clock transition which signifies that a page boundary in the
memory has been crossed and that new data is not avail-
able. The clock transition at point F does cause a burst
read of data D128 because the RDY signal goes high after
the clock transition indicating that new data is available. As
long as the BAA signal is low, additional clock transitions,
like at point G, will continue to result in burst reads until the
next page boundary is crossed between word D255 and
D256.
COMMAND SEQUENCES:
The device powers on in the
read mode. Command sequences are used to place the
device in other operating modes such as program and
erase. The command sequences are written by applying a
low pulse on the WE input with CE low and OE high. Prior
to the low going pulse on the WE signal, the address input
must be latched by a low to high transition on the AVD sig-
nal. Valid data is asserted when the WE signal is low and
latched on the rising edge of the WE pulse. The addresses
used in the command sequences are not affected by enter-
ing the command sequences.
RESET:
A RESET input pin is provided to ease some sys-
tem applications. When RESET is at a logic high level, the
device is in its standard operating mode. A low level on the
RESET pin halts the present device operation and puts the
outputs of the device in a high impedance state. When a
high level is reasserted on the RESET pin, the device
returns to Read or Standby mode, depending upon the
state of the control pins. By applying a 12 ± 0.5V input sig-
nal on the RESET pin any sector can be reprogrammed
even if the sector lockout feature has been enabled.
ERASE:
Before a word can be reprogrammed it must be
erased. The erased state of the memory bits is a logical “1”.
The entire memory can be erased by using the Chip Erase
command or individual sectors can be erased by using the
Sector Erase commands.
CHIP ERASE:
Chip Erase is a six bus cycle operation. The
automatic Erase begins on the rising edge of the last WE
pulse. Chip Erase does not alter the data of the protected
sectors. After the full chip Erase the device will return back
to the read mode. The hardware reset during Chip Erase
will stop the Erase but the data will be of unknown state.
Any command during chip Erase except erase suspend will
be ignored.
SECTOR ERASE:
As an alternative to a full chip erase, the
device is organized into 40 sectors that can be individually
erased. The Sector Erase command is a six bus cycle
operation. The sector whose address is valid at the sixth
falling edge of WE will be erased provided the given sector
has not been protected.
WORD PROGRAMMING:
The device is programmed on a
word by word basis. Programming is accomplished via the
internal device command register and is a four bus cycle
operation. The programming address and data are latched
in the fourth cycle. The device will automatically generate
the required internal programming pulses. Please note that
a “0” cannot be programmed back to a “1”; only Erase oper-
ations can convert “0”s to “1”s. During the programming
mode, the clock signal must be held low or high and cannot
toggle.
SECTOR PROGRAMMING LOCKOUT:
Each sector has a
programming lockout feature. This feature prevents pro-
gramming of data in the designated sectors once the fea-
ture has been enabled. The sectors that are locked out can
contain secure code that can bring up the system. Enabling
the lockout feature will allow the boot code to stay in the
device while data in the rest of the memory is updated. This
feature does not have to be activated; any sector’s usage
as a write protected region is optional to the user. Once the
feature is enabled, the data in the protected sector can no
longer be erased or programmed when input levels of 5.5V
or less are used. Data in the remaining sectors can still be
changed through the regular programming method. To acti-
vate the lockout feature, a series of six program commands
to specific addresses with specific data must be performed.
SECTOR LOCKOUT DETECTION:
A software method is
available to determine if programming of a sector is locked
out. When the device is in the software product identifica-
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