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參數(shù)資料
| 型號： | ATF1516ASL |
| 廠商： | Atmel Corp. |
| 英文描述： | High-performance EE-based CPLD(高性能可電擦除復(fù)雜可編程邏輯器件(CPLD)) |
| 中文描述： | 高性能電子工程為基礎(chǔ)的CPLD（高性能可電擦除復(fù)雜可編程邏輯器件（CPLD）實(shí)現(xiàn)） |
| 文件頁數(shù)： | 1/13頁 |
| 文件大?。?/td> | 254K |
| 代理商： | ATF1516ASL |
1
High-
performance
EE-based CPLD
ATF1516AS
ATF1516ASL
Preliminary
Features
High-density, High-performance, Electrically-erasable Complex
Programmable Logic Device
– 256 Macrocells
– 5 Product Terms per Macrocell, Expandable up to 40 per Macrocell
– 160, 192, 208-pins
– 10 ns Maximum Pin-to-pin Delay
– Registered Operation Up To 100 MHz
– Enhanced Routing Resources
Flexible Logic Macrocell
–
D/T/Latch Configurable Flip Flops
–
Global and Individual Register Control Signals
–
Global and Individual Output Enable
–
Programmable Output Slew Rate
–
Programmable Output Open Collector Option
–
Maximum Logic utilization by burying a register within a COM output
Advanced Power Management Features
–
Automatic 3 mA Standby for
“
L
”
Version (Maximum)
–
Pin-controlled 4 mA Standby Mode (Typical)
–
Programmable Pin-Keeper Inputs and I/Os
–
Reduced-power Feature Per Macrocell
Available in Commercial and Industrial Temperature Ranges
Available in 160-lead PQFP, 192-pin PGA, and 208-lead RQFP Packages
Advanced EE Technology
–
100% Tested
–
Completely Reprogrammable
–
10,000 Program/Erase Cycles
–
20 Year Data Retention
–
2000V ESD Protection
–
200 mA Latch-up Immunity
JTAG Boundary-scan Testing to IEEE Std. 1149.1-1990 and 1149.1a-1993 Supported
Fast In-System Programmability (ISP) via JTAG
PCI-compliant
3.3 or 5.0V I/O pins
Security Fuse Feature
Enhanced Features
Improved Connectivity (Additional Feedback Routing, Alternate Input Routing)
Output Enable Product Terms
D-latch Mode
Combinatorial Output with Registered Feedback within any Macrocell
Three Global Clock Pins
ITD (Input Transition Detection) Circuits on Global Clocks, Inputs and I/O
Fast Registered Input from Product Term
Programmable
“
Pin-Keeper
”
Option
V
CC
Power-up Reset Option
Pull-up Option on JTAG Pins TMS and TDI
Advanced Power Management Features
–
Edge Controlled Power Down
“
L
”
–
Individual Macrocell Power Option
–
Disable ITD on Global Clocks, Inputs and I/O
Rev. 0994C
–
09/99
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