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參數(shù)資料
| 型號(hào)： | ATF1516ASL |
| 廠商： | Atmel Corp. |
| 英文描述： | High-performance EE-based CPLD(高性能可電擦除復(fù)雜可編程邏輯器件(CPLD)) |
| 中文描述： | 高性能電子工程為基礎(chǔ)的CPLD（高性能可電擦除復(fù)雜可編程邏輯器件（CPLD）實(shí)現(xiàn)） |
| 文件頁(yè)數(shù)： | 7/13頁(yè) |
| 文件大小： | 254K |
| 代理商： | ATF1516ASL |
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ATF1516AS(L)
7
Input Test Waveforms and
Measurement Levels
r
R
, t
F
= 1.5 ns typical
Output AC Test Loads:
Note:
*Numbers in parenthesis refer to 3.0V operating condi-
tions (preliminary).
Power Down Mode
The ATF1516AS includes two pins for optional pin con-
trolled power down feature.
When this mode is enabled, the
PD pin acts as the power down pin. When the PD1 and
PD2 pin is high, the device supply current is reduced to
less than 3 mA. During power down, all output data and
internal logic states are latched and held. Therefore, all
registered and combinatorial output data remain valid. Any
outputs which were in a Hi-Z state at the onset will remain
at Hi-Z. During power down, all input signals except the
power down pin are blocked. Input and I/O hold latches
remain active to insure that pins do not float to indetermi-
nate levels, further reducing system power. The power
down pin feature is enabled in the logic design file. Designs
using either power down pin may not use the PD pin logic
array input. However, all other PD pin as macrocell
resources may still be used, including the buried feedback
and foldback product term array inputs.
(3.0V)*
(703 )*
(8060 )*
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ATF1516ASL-20QC160 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:High Performance EE-Based CPLD |
| ATF1516ASL-20QHC208 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:High Performance EE-Based CPLD |
| ATF1516ASL-20QHI208 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:High Performance EE-Based CPLD |
| ATF1516ASL-20QI160 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:High Performance EE-Based CPLD |
| ATF1516ASL-20UC192 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:High Performance EE-Based CPLD |
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