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參數(shù)資料
| 型號(hào)： | ATF1516ASL |
| 廠商： | Atmel Corp. |
| 英文描述： | High-performance EE-based CPLD(高性能可電擦除復(fù)雜可編程邏輯器件(CPLD)) |
| 中文描述： | 高性能電子工程為基礎(chǔ)的CPLD（高性能可電擦除復(fù)雜可編程邏輯器件（CPLD）實(shí)現(xiàn)） |
| 文件頁(yè)數(shù)： | 8/13頁(yè) |
| 文件大?。?/td> | 254K |
| 代理商： | ATF1516ASL |
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ATF1516AS(L)
8
JTAG-BST Overview
The JTAG boundary-scan testing is controlled by the Test
Access Port (TAP) controller in the ATF1516AS. The
boundary-scan technique involves the inclusion of a shift-
register stage (contained in a boundary-scan cell) adjacent
to each component so that signals at component bound-
aries can be controlled and observed using scan testing
principles. Each input pin and I/O pin has its own boundary
scan cell (BSC) in order to support boundary scan testing.
The ATF1516AS does not currently include a Test Reset
(TRST) input pin because the TAP controller is automati-
cally reset at power up. The six JTAG BST modes
supported include: SAMPLE/PRELOAD, EXTEST,
BYPASS, IDCODE. BST on the ATF1516AS is imple-
mented using the Boundary Scan Definition Language
(BSDL) described in the JTAG specification (IEEE Stan-
dard 1149.1). Any third party tool that supports the BSDL
format can be used to perform BST on the ATF1516AS.
The ATF1516AS also has the option of using four JTAG-
standard I/O pins for in-system programming (ISP). The
ATF1516AS is programmable through the four JTAG pins
using programming compatible with the IEEE JTAG Stan-
dard 1149.1. Programming is performed by using 5V TTL-
level programming signals from the JTAG ISP interface.
The JTAG feature is a programmable option. If JTAG (BST
or ISP) is not needed, then the four JTAG control pins are
available as I/O pins.
JTAG Boundary Scan Cell (BSC)
Testing
The ATF1516AS contains up to 160 I/O pins and 4 input
pins, depending on the device type and package type
selected. Each input pin and I/O pin has its own boundary
scan cell (BSC) in order to support boundary scan testing
as described in detail by IEEE Standard 1149.1. Typical
BSC consists of three capture registers or scan registers
and up to two update registers. There are two types of
BSCs, one for input or I/O pin, and one for the macrocells.
The BSCs in the device are chained together through the
capture registers. Input to the capture register chain is fed
in from the TDI pin while the output is directed to the TDO
pin. Capture registers are used to capture active device
data signals, to shift data in and out of the device and to
load data into the update registers. Control signals are gen-
erated internally by the JTAG TAP controller. The BSC
configuration for the input and I/O pins and macrocells are
shown below.
BSC Configuration Pins and
Macrocells (except JTAG TAP Pins)
Note:
The ATF1516AS has pull-up option on TMS and TDI
pins. This feature is selected as a design option.
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| ATF1516ASL-20QC160 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:High Performance EE-Based CPLD |
| ATF1516ASL-20QHC208 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:High Performance EE-Based CPLD |
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| ATF1516ASL-20QI160 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:High Performance EE-Based CPLD |
| ATF1516ASL-20UC192 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:High Performance EE-Based CPLD |
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