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參數(shù)資料
| 型號： | ATF1516ASL |
| 廠商： | Atmel Corp. |
| 英文描述： | High-performance EE-based CPLD(高性能可電擦除復(fù)雜可編程邏輯器件(CPLD)) |
| 中文描述： | 高性能電子工程為基礎(chǔ)的CPLD（高性能可電擦除復(fù)雜可編程邏輯器件（CPLD）實(shí)現(xiàn)） |
| 文件頁數(shù)： | 5/13頁 |
| 文件大?。?/td> | 254K |
| 代理商： | ATF1516ASL |
ATF1516AS(L)
5
Programmable Pin-Keeper Option
for Inputs and I/Os
The ATF1516AS offers the option of programming all input
and I/O pins so that
“
pin keeper
”
circuits can be utilized.
When any pin is driven high or low and then subsequently
left floating, it will stay at that previous high or low level.
This circuitry prevents unused input and I/O lines from
floating to intermediate voltage levels, which cause unnec-
essary power consumption and system noise. The keeper
circuits eliminate the need for external pull-up resistors and
eliminate their DC power consumption.
Input Diagram
I/O Diagram
Speed/Power Management
The ATF1516AS has several built-in speed and power
management features. The ATF1516AS contains circuitry
that automatically puts the device into a low power stand-
by mode when no logic transitions are occurring. This not
only reduces power consumption during inactive periods,
but also provides a proportional power savings for most
applications running at system speeds below 50 MHz.
To further reduce power, each ATF1516AS macrocell has
a Reduced Power bit feature. This feature allows individual
macrocells to be configured for maximum power savings.
This feature may be selected as a design option.
All ATF1516ASs also have an optional power down mode.
In this mode, current drops to below 10 mA. When the
power down option is selected, either PD1 or PD2 pins (or
both) can be used to power down the part. The power down
option is selected in the design source file. When enabled,
the device goes into power down when either PD1 or PD2
is high. In the power down mode, all internal logic signals
are latched and held, as are any enabled outputs.
All pin transitions are ignored until the PD pin is brought
low. When the power down feature is enabled, the PD1 or
PD2 pin cannot be used as a logic input or output. How-
ever, the pin
’
s macrocell may still be used to generate
buried foldback and cascade logic signals.
All Power-Down AC Characteristic parameters are com-
puted from external input or I/O pins, with Reduced Power
Bit turned on. For macrocells in reduced-power mode
(Reduced power bit turned on), the reduced power adder,
tRPA, must be added to the AC parameters, which include
the data paths t
LAD
, t
LAC
, t
IC
, t
ACL
, t
ACH
and t
SEXP
.
Each output also has individual slew rate control. This may
be used to reduce system noise by slowing down outputs
that do not need to operate at maximum speed. Outputs
default to slow switching, and may be specified as fast
switching in the design file.
Design Software Support
ATF1516AS designs are supported by several third party
tools. Automated fitters allow logic synthesis using a variety
of high level description languages and formats.
Power-up Reset
The ATF1516AS has a power-up reset option at two differ-
ent voltage trip levels when the device is being powered
down. Within the fitter, or during a conversion, if the
“
power-reset
”
option is turned
“
on
”
(which is the default
option), the trip levels during power up or power down is at
2.8V. The user can change this default option from
“
on
”
to
“
off
”
(within the fitter or specify it as a switch during conver-
sion). When this is done, the voltage trip level during
power-down changes from 2.8V to 0.7V. This is to ensure a
robust operating environment.
The registers in the ATF1516AS are designed to reset dur-
ing power up. At a point delayed slightly from V
CC
crossing
V
RST
, all registers will be reset to the low state. The output
state will depend on the polarity of the buffer.
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