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參數(shù)資料
| 型號(hào)： | ATF1516ASL |
| 廠商： | Atmel Corp. |
| 英文描述： | High-performance EE-based CPLD(高性能可電擦除復(fù)雜可編程邏輯器件(CPLD)) |
| 中文描述： | 高性能電子工程為基礎(chǔ)的CPLD（高性能可電擦除復(fù)雜可編程邏輯器件（CPLD）實(shí)現(xiàn)） |
| 文件頁(yè)數(shù)： | 3/13頁(yè) |
| 文件大小： | 254K |
| 代理商： | ATF1516ASL |
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ATF1516AS(L)
3
Description
The ATF1516AS is a high performance, high density Com-
plex Programmable Logic Device (CPLD) which utilizes
Atmel
’
s proven electrically erasable technology. With 256
logic macrocells and up to 164 inputs, it easily integrates
logic from several TTL, SSI, MSI, LSI and classic PLDs.
The ATF1516AS
’
s enhanced routing switch matrices
increase usable gate count, and increase odds of success-
ful pin-locked design modifications.
The ATF1516AS has up to 160 bi-directional I/O pins and 4
dedicated input pins, depending on the type of device pack-
age selected. Each dedicated pin can also serve as a
global control signal; register clock, register reset or output
enable. Each of these control signals can be selected for
use individually within each macrocell.
Each of the 256 macrocells generates a buried feedback,
which goes to the global bus. Each input and I/O pin also
feeds into the global bus. The switch matrix in each logic
block then selects 40 individual signals from the global bus.
Each macrocell also generates a foldback logic term, which
goes to a regional bus. Cascade logic between macrocells
in the ATF1516AS allows fast, efficient generation of com-
plex logic functions. The ATF1516AS contains eight such
logic chains, each capable of creating sum term logic with a
fan in of up to 40 product terms
The ATF1516AS macrocell, shown in Figure 1, is flexible
enough to support highly complex logic functions operating
at high speed. The macrocell consists of five sections:
product terms and product term select multiplexer;
OR/XOR/CASCADE logic; a flip-flop; output select and
enable; and logic array inputs.
Unused Macrocells are automatically disabled by the com-
piler to decrease power consumption. A Security Fuse,
when programmed, protects the contents of the
ATF1516AS. Two bytes (16 bits) of User Signature are
accessible to the user for purposes such as storing project
name, part number, revision or date. The User Signature is
accessible regardless of the state of the Security Fuse.
The ATF1516AS device is an In-System Programmable
(ISP) device. It uses the industry standard 4-pin JTAG
interface (IEEE Std. 1149.1), and is fully compliant with
JTAG
’
s Boundary Scan Description Language (BSDL). ISP
allows the device to be programmed without removing it
from the printed circuit board. In addition to simplifying the
manufacturing flow, ISP also allows design modifications to
be made in the field via software.
Figure 1.
ATF1516AS Macrocell
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