參數(shù)資料
型號: AS4LC8M8S0-10TC
廠商: ALLIANCE SEMICONDUCTOR CORP
元件分類: DRAM
英文描述: 3.3V 4Mx16 and 8Mx8 CMOS synchronous DRAM
中文描述: 8M X 8 SYNCHRONOUS DRAM, 6 ns, PDSO54
封裝: 0.400 INCH, PLASTIC, TSOP2-54
文件頁數(shù): 8/24頁
文件大?。?/td> 566K
代理商: AS4LC8M8S0-10TC
8
ALLIANCE SEMICONDUCTOR
7/5/00
AS4LC4M16S0
AS4LC16M4S0
AC parameters common to all waveforms
Sym
t
RRD
Row active to row active delay
t
RCD
RAS to CAS delay time
t
RP
Row precharge
t
RAS
Row active
tRC Row cycle time
Last data in to new column
address delay
t
RDL
Last data in to row precharge
t
BDL
Last data in to burst stop
Column address to column
address delay
Parameter
CAS
latency
-75
-8
-10F
-10
Unit Notes
ns
ns
ns
ns
ns
Min Max
15
20
20
44
66
Min
20
20
20
50
70
Max
Min
20
20
20
50
70
Max
Min
20
30
30
60
90
Max
1
1
1
1
1
t
CDL
1
1
1
1
CLK
2
2
1
2
1
2
1
2
1
CLK
CLK
2
2
t
CCD
1
1
1
1
CLK
3
t
CK
CLK cycle time
3
2
3
2
3
2
7.5
10
5.4
6
2.7
3
2.5
2.5
1.5
0.8
1
0.8
1.5
6
6
8
10
6
6
3
3
3
3
2
1
1
1
2
7
7
10
15
6
6
3
3
3
3
2
1
1
1
2
7
7
10
15
6
6
3
3
3
3
2
1
1
1
2
7
7
ns
4
4
t
AC
CLK to valid output delay @ 50pF
ns
4,5,7
4,5,7
4,5,7
4,5,7
6
6
6
6
5
t
OH
Output data hold time @ 50 pF
ns
t
CH
t
CL
t
AS
t
AH
t
SLZ
CLK to output in low Z
CLK high pulse width
CLK low pulse width
Add setup time
Add hold time
ns
ns
ns
ns
ns
t
SHZ
CLK to output in high Z
3
2
ns
t
CKH
CKE hold time
t
CKS
CKE setup time
CS, RAS, CAS, WE, DQM hold
time
CS, RAS, CAS, WE, DQM setup
time
t
DH
Data in hold time
t
DS
Data in setup time
ns
ns
t
CMH
0.8
1
1
1
ns
t
CMS
1.5
2
2
2
ns
0.8
1.5
1
2
1
2
1
2
ns
ns
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