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參數(shù)資料
| 型號： | AS4C4M4EOQ |
| 廠商： | Alliance Semiconductor Corporation |
| 英文描述： | 4M × 4 CMOS QuadCAS DRAM(EDO) Family(4M × 4 CMOS QuadCAS動態(tài)RAM（擴展數(shù)據(jù)總線）) |
| 中文描述： | 4米× 4的CMOS QuadCAS的DRAM（江戶）家庭（4米× 4的CMOS QuadCAS動態(tài)隨機存儲器（擴展數(shù)據(jù)總線）） |
| 文件頁數(shù)： | 5/16頁 |
| 文件大小： | 384K |
| 代理商： | AS4C4M4EOQ |
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Parameter
Symbol Test conditions
0V
≤
V
in
≤
V
CC
(max)
Pins not under test = 0V
D
OUT
disabled, 0V
≤
V
out
≤
V
CC
(max)
RAS, UCAS, LCAS, Address cycling;
t
RC
=min
RAS = UCAS = LCAS
≥
V
IH
,
all other inputs at V
IH
or V
IL
-50
-60
Unit
Notes
Min
Max
Min
Max
Input leakag
e c
urrent
I
IL
-5
+5
-5
+5
μ
A
Output leakage current I
OL
-5
+5
-5
+5
μ
A
Operating power
supply current
TTL standby power
supply current
Average power supply
current, RAS refresh
mode or CBR
EDO page mode
average power supply
current
CMOS standby power
supply current
I
CC1
–
85
–
75
mA
4,5
I
CC2
–
2.0
–
2.0
mA
I
CC3
RAS cycling, UCAS = LCAS
≥
V
IH
,
t
RC
= min of RAS low after XCAS low.
–
80
–
70
mA
4
I
CC4
RAS = V
IL
, UCAS or LCAS,
address cycling: t
HPC
= min
–
85
–
75
mA
4, 5
I
CC5
RAS = UCAS = LCAS = V
CC
- 0.2V
F = 0
I
OUT
= -2.0 mA
I
OUT
= 2 mA
RAS, UCAS or LCAS cycling, t
RC
=
min
RAS = UCAS = LCAS
≤
0.2V
WE = OE = V
CC
- 0.2V
all other inputs at 0.2V or V
CC
-
0.2V
–
200
–
200
μA
Output voltage
V
OH
V
OL
2.4
–
–
2.4
–
–
V
V
0.4
0.4
CAS before RAS refresh
current
I
CC6
–
80
–
70
mA
Self refresh current
I
CC7
–
0.3
–
0.3
mA
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