- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄381310 > AS4C4M4EOQ (Alliance Semiconductor Corporation) 4M × 4 CMOS QuadCAS DRAM(EDO) Family(4M × 4 CMOS QuadCAS動態(tài)RAM（擴(kuò)展數(shù)據(jù)總線）) PDF資料下載
參數(shù)資料
| 型號： | AS4C4M4EOQ |
| 廠商： | Alliance Semiconductor Corporation |
| 英文描述： | 4M × 4 CMOS QuadCAS DRAM(EDO) Family(4M × 4 CMOS QuadCAS動態(tài)RAM（擴(kuò)展數(shù)據(jù)總線）) |
| 中文描述： | 4米× 4的CMOS QuadCAS的DRAM（江戶）家庭（4米× 4的CMOS QuadCAS動態(tài)隨機(jī)存儲器（擴(kuò)展數(shù)據(jù)總線）） |
| 文件頁數(shù)： | 2/16頁 |
| 文件大小： | 384K |
| 代理商： | AS4C4M4EOQ |
$6
7
&
7
0
7
(24
$6
7
&
7
0
7
(
4
4
$GYDQFH
#
LQIRUPDWLRQ
5
#
$//,$1&(
#
6(0,&21'8&725
','
#440633370
$
1#4257233
)XQFWLRQDO
#
GHVFULSWLRQ
The 4C4M4EOQ, and AS4C4M4E1Q are high performance 16-megabit CMOS Quad CAS Dynamic Random Access Memories (DRAM)
organized as 4,194,304 words × 4 bits. The devices are fabricated using advanced CMOS technology and innovative design techniques
resulting in high speed, extremely low power and wide operating margins at component and system levels. The Alliance 16Mb DRAM amily
is optimized for use as main memory in PC, workstation, router and switch applications.
These products feature a high speed page mode operation where read and write operations within a single row (or page) can be executed at
very high speed by toggling column addresses within tha row. Row and column addresses are alternately latched into input buffers using the
falling edge of RAS and CAS inputs respectively. Also, RAS is used to make the column address latch transparent, enabling application of
column addresses prior to CAS assertion.
Extended data out (EDO) read mode enables 50 MHz operation using 50 ns devices. Four individual CAS pins allow for separate I/O
operation which enables the device to operate in parity mode. In contrast to 'fast page mode' devices, data remains active on outputs after
CAS is de-asserted high, giving system logic more time to latch the data. Use OE and WE to control output impedance and prevent bus
contention during read-modify-write and shared bus applications. Outputs also go to high impedance at the last occurrance of RAS and CAS
going high.
Refresh on the 4096 address combinations of A0 to A11 must be performed every 64 ms using:
RAS-only refresh: RAS is asserted while CAS is held high. Each of the 4096 rows must be strobed. Outputs remain high impedence.
Hidden refresh: CAS is held low while RAS is toggled. Refresh address is generated internally. Outputs remain low impedence with
previous valid data.
CAS-before-RAS refresh (CBR): At least one CAS is asserted prior to RAS. Refresh address is generated internaly.
Outputs are high-impedence (OE and WE are don't care).
Normal read or write cycles refresh the row being accessed.
Self-refresh cycles
Refresh on the 2048 address combinations of A0 to A10 must be performed every 32 ms using:
RAS-only refresh: RAS is asserted while CAS is held high. Each of the 2048 rows must be strobed. Outputs remain high impedence.
Hidden refresh: CAS is held low while RAS is toggled. Refresh address is generated internally. Outputs remain low impedence with
previous valid data.
CAS-before-RAS refresh (CBR): At least one CAS is asserted prior to RAS. Refresh address is generated internaly.
Outputs are high-impedence (OE and WE are don't care).
Normal read or write cycles refresh the row being accessed.
Self-refresh cycles
The 4C4M4EOQ and AS4C4M4E1Q are available in the standard 28-pin plastic SOJ and 28-pin plastic TSOP packages. The 4C4M4EOQ and
AS4C4M4E1Q operate with a single power supply of 5V ± 0.5V. All provide TTL compatible inputs and outputs.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AS4C4M4F0 | 5V 4M×4 CMOS DRAM （Fast Page Mode)(5V 4M×4 CMOS 動態(tài)RAM（快速頁面模式）) |
| AS4C4M4F1 | 5V 4M×4 CMOS DRAM （Fast Page Mode)(5V 4M×4 CMOS 動態(tài)RAM（快速頁面模式）) |
| AS4C4M4F1Q | 5V 4M×4 CMOS QuadCAS DRAM （Fast Page Mode)(5V 4M×4 CMOS QuadCAS 動態(tài)RAM（快速頁面模式）) |
| AS4C4M4FOQ | 5V 4M×4 CMOS QuadCAS DRAM （Fast Page Mode)(5V 4M×4 CMOS QuadCAS 動態(tài)RAM（快速頁面模式）) |
| AS4LC1M16E5 | 3V 1M×16 CMOS DRAM (EDO)(3V 1M×16 CMOS動態(tài)RAM（擴(kuò)展數(shù)據(jù)總線)) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AS4C4M4F0 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:5V 4M x 4 CMOS DRAM (Fast Page mode) |
| AS4C4M4F0-50 | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:5V 4M×4 CMOS DRAM (Fast Page mode) |
| AS4C4M4F0-50JC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x4 Fast Page Mode DRAM |
| AS4C4M4F0-50JI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x4 Fast Page Mode DRAM |
| AS4C4M4F0-50TC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x4 Fast Page Mode DRAM |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。