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6
Am79C978
FIFO Burst Write At Start Of Unaligned Buffer 58
FIFO DMA Transfers 57
Flow, LAPP 2
FMDC Values 169
FRAME 26
Frame Format at the MII Interface Connection 35
Framing 65, 75
Full-Duplex Link Status LED Support 74
Full-Duplex Operation 73
G
GENERAL DESCRIPTION 2
GNT 26
H
H_RESET 94
Header AID Remote Control Word Commands 81
Home Networking Controller 1
Home Phoneline Networking Alliance (HomeP-
NA) 1
HomePNA Analog Ground 32
HomePNA Analog Power 32
HomePNA Digital Power 32
HomePNA PHY Framing 76
HomePNA PHY Network Interface 31
HomePNA Physical Layer (PHY) 1
HPR0
HomePNA PHY MII Control (Register 0) 179
HPR1
HomePNA PHY MII Status (Register 1) 180
HPR16
HomePNA PHY Control (Register 16) 182,
183
HPR18 and HPR19
HomePNA PHY TxCOMM (Registers 18 and
19) 183
HPR2 and HPR3
HomePNA PHY MII PHY ID (Registers 2 and
3) 181
HPR20 and HPR21
HomePNA PHY RxCOMM (Registers 20 and
21) 184
HPR22
HomePNA PHY AID (Register 22) 184
HPR23
HomePNA PHY Noise Control (Register 23)
184
HPR24
HomePNA PHY Noise Control 2 (Register 24)
185
HPR25
HomePNA PHY Noise Statistics (Register 25)
185
HPR26
HomePNA PHY Event Status (Register 26)
186
HPR27
HomePNA PHY Event Status (Register 27)
186
HPR28
HomePNA PHY ISBI Control (Register 28)
186
HPR29
HomePNA PHY TX Control (Register 29) 187
HPR4-HPR7
HomePNA PHY Auto-Negotiation (Registers
4 - 7) 181
HRTXRXP/HRTXRXN 31
I
I/O Buffer Ground (17 Pins) 32
I/O Buffer Power (7 Pins) 32
I/O Map In DWord I/O Mode (DWIO = 1) 98
I/O Map in DWord I/O Mode (DWIO = 1) 98
I/O Map In Word I/O Mode (DWIO = 0) 97
I/O Registers 96
I/O Resources 95
IDSEL 26
IEEE 1149.1 (1990) Test Access Port Interface 31,
91
IEEE 1149.1 Supported Instruction Summary 91
IEEE 802.3 Frame And Length Field Transmis-
sion Order 73
IEEE 802.3u 2
Initialization 59
Initialization Block 198
Initialization Block (SSIZE32 = 0) 198
Initialization Block (SSIZE32 = 1) 198
Initialization Block DMA Transfers 52
Initialization Block Read In Burst Mode 53
Initialization Block Read In Non-Burst Mode 53
Initialization Device Select 26
Initiator Ready 27
Input Setup and Hold Timing 230
Instruction Register and Decoding Logic 91
INTA 27
Integrated Controllers 15
integrated PCI Ethernet controller 2
Integrated Repeater/Hub Devices 15
Inter Packet Gap (IPG) 2
Interface Pin Assignment 161