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216
Am79C978
Am79C978 Programmable Registers (Continued)
Register
CSR76
CSR78
CSR80
Contents
RCVRL: RCV Descriptor Ring length
XMTRL: XMT Descriptor Ring length
FIFO threshold and DMA burst control (DEFAULT = 2810)
8000 Reserved
4000 Reserved
bits [13:12] = RCVFW, Receive FIFO Watermark
0000 Request DMA when 16 bytes are present
1000 Request DMA when 64 bytes are present
2000 Request DMA when 112 bytes are present
3000 Reserved
bits [11:10] = XMTSP, Transmit Start Point
0000 Start transmission after 20/36 (No SRAM/SRAM) bytes have been written
0400 Start transmission after 64 bytes have been written
0800 Start transmission after 128 bytes have been written
0C00 Start transmission after 220 max/Full Packet (No SRAM/SRAM with UFLO bit set) bytes
have been written
bits [9:8] = XMTFW, Transmit FIFO Watermark
0000 Start DMA when 16 write cycles can be made
0100 Start DMA when 32 write cycles can be made
0200 Start DMA when 64 write cycles can be made
0300 Start DMA when 128 write cycles can be made
bits [7:0] = DMA Burst Register
Chip ID (Contents = v12626003; v = Version Number)
Missed Frame Count
Receive Collision Count
OnNow Miscellaneous
8000
--
4000
--
2000
--
1000
--
0100
LCDET
Receive Frame Alignment Control
8000
--
4000
--
2000
--
1000
--
0100
--
BMU Test Register (DEFAULT = 0000)
8000
--
4000
--
2000
--
1000
--
0100
--
MAC Enhanced Configuration Control (DEFAULT = 603c)
bits [15:8] = IPG, InterPacket Gap (Default = 60xx, 96 bit times)
bits [8:0] = IFS1, InterFrame Space Part 1 (Default = xx3c, 60 bit times)
CSR88~89
CSR112
CSR114
CSR116
0800
0400
0200 PME_EN_OVR
--
--
0080
0040
0020
0010
PMAT
EMPPLBA
MPMAT
MPPEN
0008
0004
0002
0001
RWU_DRIVER
RWU_GATE
RWU_POL
RST_POL
CSR122
0800
0400
0200
--
--
--
0080
0040
0020
0010
--
--
--
--
0008
0004
0002
0001
--
--
--
RCVALGN
CSR124
0800
0400
0200
--
--
--
0080
0040
0020
0010
--
--
--
--
0008
0004
0002
0001
--
RPA
--
--
CSR125