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參數(shù)資料
| 型號(hào)： | AM79C978 |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | Single-Chip 1/10 Mbps PCI Home Networking Controller |
| 中文描述： | 單芯片的1 / 10 Mbps的家庭網(wǎng)絡(luò)控制器的PCI |
| 文件頁(yè)數(shù)： | 166/261頁(yè) |
| 文件大?。?/td> | 3803K |
| 代理商： | AM79C978 |
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166
Am79C978
5-3
EBCS
Expansion Bus Clock Source.
These bits are used to select the
source of the fundamental clock
to drive the SRAM and Expansion
ROM access cycles. Table 42
shows the selected clock source
for the various values of EBCS.
Note that the actual frequency
that the Expansion Bus access
cycles run at is a function of both
the
EBCS
and
(BCR27, bits 2-0) bit field set-
tings. When EBCS is set to either
the PCI clock or the Time Base
clock, no external clock source is
required as the clocks are routed
internally and the EBCLK pin
should be pulled to VDD through
a resistor.
CLK_FAC
Read accessible always; write
accessible only when the STOP
bit is set. EBCS is set to 000b
(PCI
clock
selected) during
H_RESET and is unaffected by
S_RESET or the STOP bit.
Note
: The clock frequency driv-
ing the Expansion Bus access cy-
cles that results from the settings
of the EBCS and CLK FAC bits
must not exceed 33 MHz at any
time. When EBCS is set to either
the PCI clock or the Time Base
clock, no external clock source is
required because the clocks are
routed internally and the EBCLK
pin should be pulled to VDD
through a resistor.
CAUTION: Care should be ex-
ercised when choosing the PCI
clock pin because of the nature
of the PCI clock signal. The PCI
specification states that the
PCI clock can be stopped. If
that can occur while it is being
used for the Expansion Bus
clock data, corruption will re-
sult.
CAUTION: The Time Base
Clock will not support 100
Mbps operation and should
only be selected in 10 Mbps-
only configurations.
CAUTION: The external clock
source used to drive the
EBCLK pin must be a continu-
ous clock source at all times.
2-0
CLK_FAC
Clock Factor. These bits are used
to select whether the clock select-
ed by EBCS is used directly or if it
is divided down to give a slower
clock for running the Expansion
Bus access cycles. The possible
factors are given in Table 43.
Read accessible always; write
accessible only when the STOP
bit is set. CLK_FAC is set to 000b
during H_RESET and is unaffect-
ed by S_RESET or STOP.
BCR28: Expansion Bus Port Address Lower (Used
for Flash/EPROM and SRAM Accesses)
Bit
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-0
EPADDRL
Expansion Port Address Lower.
This address is used to provide
addresses for the Flash and
SRAM port accesses.
SRAM accesses are started
when a read or write is performed
on BCR30 and the FLASH (BCR
29, bit 15) is set to 0. During
SRAM accesses only bits in the
EPADDRL are valid. Since all
SRAM accesses are word orient-
ed only, EPADDRL[0] is the least
significant word address bit. On
Table 42.
Expansion Bus Clock Source
CLK pin (PCI Clock)
Time Base Clock
EBCLK pin
Reserved
Reserved
EBCS Values
EBCS
000
001
010
011
1XX
Table 43.
CLK_FAC Values
Clock Factor
CLK_FAC
000
001
010
011
1XX
1
1/2 (divide by 2)
Reserved
1/4 (divide by 4)
Reserved
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C978A | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Single-Chip 1/10 Mbps PCI Home Networking Controller |
| AM79C978AKC\\W | 制造商:Advanced Micro Devices 功能描述: |
| AM79C978AKC\W | 制造商:Advanced Micro Devices 功能描述: |
| AM79C978AKCW | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Single-Chip 1/10 Mbps PCI Home Networking Controller |
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