參數(shù)資料
型號: AM49PDL640AG
英文描述: 120NS, FLATPACK, 883C; LEV B COMPLIANT(EEPROM)
中文描述: Am49PDL640AG -堆疊式多芯片封裝(MCP)閃存和SRAM
文件頁數(shù): 57/69頁
文件大?。?/td> 1062K
代理商: AM49PDL640AG
August 5, 2003
Am49PDL640AG
55
P R E L I M I N A R Y
FLASH AC CHARACTERISTICS
Alternate CE#f Controlled Erase and Program Operations
1. Not 100% tested.
2. See the “Deep Power Down Mode” section for more information.
Parameter
Speed Options
JEDEC
Std.
Description
70
85
Unit
t
AVAV
t
WC
Write Cycle Time (Note 1)
Min
70
85
ns
t
AVWL
t
AS
Address Setup Time
Min
0
ns
t
ELAX
t
AH
Address Hold Time
Min
45
ns
t
DVEH
t
DS
Data Setup Time
Min
35
ns
t
EHDX
t
DH
Data Hold Time
Min
0
ns
t
GHEL
t
GHEL
Read Recovery Time Before Write
(OE# High to WE# Low)
Min
0
ns
t
WLEL
t
WS
WE# Setup Time
Min
0
ns
t
EHWH
t
WH
WE# Hold Time
Min
0
ns
t
ELEH
t
CP
CE# Pulse Width
Min
35
ns
t
EHEL
t
CPH
CE# Pulse Width High
Min
30
ns
t
WHWH1
t
WHWH1
Programming Operation
(Note 2)
Typ
6
μs
t
WHWH1
t
WHWH1
Accelerated Programming Operation (Note 2)
Typ
4
μs
t
WHWH2
t
WHWH2
Sector Erase Operation (Note 2)
Typ
0.2
sec
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