參數(shù)資料
型號(hào): AM49PDL640AG
英文描述: 120NS, FLATPACK, 883C; LEV B COMPLIANT(EEPROM)
中文描述: Am49PDL640AG -堆疊式多芯片封裝(MCP)閃存和SRAM
文件頁(yè)數(shù): 27/69頁(yè)
文件大?。?/td> 1062K
代理商: AM49PDL640AG
August 5, 2003
Am49PDL640AG
25
P R E L I M I N A R Y
Table 11.
Device Geometry Definition
Addresses
Data
Description
27h
0017h
Device Size = 2
N
byte
28h
29h
0001h
0000h
Flash Device Interface description (refer to CFI publication 100)
2Ah
2Bh
0000h
0000h
Max. number of byte in multi-byte write = 2
N
(00h = not supported)
2Ch
0003h
Number of Erase Block Regions within device
2Dh
2Eh
2Fh
30h
0007h
0000h
0020h
0000h
Erase Block Region 1 Information
(refer to the CFI specification or CFI publication 100)
31h
32h
33h
34h
007Dh
0000h
0000h
0001h
Erase Block Region 2 Information
(refer to the CFI specification or CFI publication 100)
35h
36h
37h
38h
0007h
0000h
0020h
0000h
Erase Block Region 3 Information
(refer to the CFI specification or CFI publication 100)
39h
3Ah
3Bh
3Ch
0000h
0000h
0000h
0000h
Erase Block Region 4 Information
(refer to the CFI specification or CFI publication 100)
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