參數(shù)資料
型號(hào): AM49PDL640AG
英文描述: 120NS, FLATPACK, 883C; LEV B COMPLIANT(EEPROM)
中文描述: Am49PDL640AG -堆疊式多芯片封裝(MCP)閃存和SRAM
文件頁數(shù): 10/69頁
文件大小: 1062K
代理商: AM49PDL640AG
8
Am49PDL640AG
August 5, 2003
P R E L I M I N A R Y
PIN DESCRIPTION
A19–A0
= 20 Address Inputs (Common)
A21–A20
= 2 Address Inputs (Flash)
DQ15–DQ0
= 16 Data Inputs/Outputs (Common)
CE#f
= Chip Enable (Flash)
CE#1s
= Chip Enable 1 (pSRAM)
CE2s
= Chip Enable 2 (pSRAM)
OE#
= Output Enable (Common)
WE#
= Write Enable (Common)
RY/BY#
= Ready/Busy Output
UB#s
= Upper Byte Control (pSRAM)
LB#s
= Lower Byte Control (pSRAM)
RESET#
= Hardware Reset Pin, Active Low
WP#/ACC
= Hardware Write Protect/
Acceleration Pin (Flash)
V
CC
f
= Flash 3.0 volt-only single power sup-
ply (see Product Selector Guide for
speed options and voltage supply
tolerances)
V
CC
s
V
SS
NC
= pSRAM Power Supply
= Device Ground (Common)
= Pin Not Connected Internally
LOGIC SYMBOL
19
16 or 8
DQ15–DQ0
A19–A0
CE#f
OE#
WE#
RESET#
UB#s
RY/BY#
WP#/ACC
A21–A20
LB#s
CE#1s
CE2s
相關(guān)PDF資料
PDF描述
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