參數(shù)資料
型號: AM49PDL640AG
英文描述: 120NS, FLATPACK, 883C; LEV B COMPLIANT(EEPROM)
中文描述: Am49PDL640AG -堆疊式多芯片封裝(MCP)閃存和SRAM
文件頁數(shù): 49/69頁
文件大小: 1062K
代理商: AM49PDL640AG
August 5, 2003
Am49PDL640AG
47
P R E L I M I N A R Y
FLASH AC CHARACTERISTICS
Hardware Reset (RESET#)
Note:
Not 100% tested.
Parameter
Description
All Speed Options
Unit
JEDEC
Std
t
Ready
RESET# Pin Low (During Embedded Algorithms)
to Read Mode (See Note)
Max
20
μ
s
t
Ready
RESET# Pin Low (NOT During Embedded
Algorithms) to Read Mode (See Note)
Max
500
ns
t
RP
RESET# Pulse Width
Min
500
ns
t
RH
Reset High Time Before Read (See Note)
Min
50
ns
t
RPD
RESET# Low to Standby Mode
Min
20
μ
s
t
RB
RY/BY# Recovery Time
Min
0
ns
RESET#
RY/BY#
RY/BY#
t
RP
t
Ready
Reset Timings NOT during Embedded Algorithms
t
Ready
CE#f, OE#
t
RH
CE#f, OE#
Reset Timings during Embedded Algorithms
RESET#
t
RP
t
RB
Figure 16.
Reset Timings
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