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| 型號： | AM42DL6404G |
| 英文描述： | 64 Mbit (8 M x 8-Bit/4 M x 16-Bit) CMOS and 4 Mbit (256 K x 16-Bit) Static RAM (Preliminary) |
| 中文描述： | 64兆位（8米× 8位/ 4米× 16位）CMOS和4兆位（256畝× 16位），靜態(tài)存儲器（初步） |
| 文件頁數(shù)： | 56/60頁 |
| 文件大小： | 956K |
| 代理商： | AM42DL6404G |
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March 4, 2002
Am42DL16x2D
55
P R E L I M I N A R Y
AC CHARACTERISTICS
Notes:
1. UB#s and LB#s controlled, CIOs must be high.
1. t
CW
is measured from CE1#s going low to the end of write.
2. t
WR
is measured from the end of write to the address change. t
WR
applied in case a write ends as CE1#s or WE# going high.
3. t
AS
is measured from the address valid to the beginning of write.
4. A write occurs during the overlap (t
WP
) of low CE#1 and low WE#. A write begins when CE1#s goes low and WE# goes low when
asserting UB#s or LB#s for a single byte operation or simultaneously asserting UB#s and LB#s for a double byte operation. A
write ends at the earliest transition when CE1#s goes high and WE# goes high. The t
WP
is measured from the beginning of write
to the end of write.
Figure 32.
SRAM Write Cycle—UB#s and LB#s Control
Address
Data Valid
UB#s, LB#s
WE#
Data In
Data Out
High-Z
High-Z
t
WC
CE1#s
CE2s
t
AW
t
BW
t
DW
t
DH
t
WR
(See Note 3)
t
AS
(See Note 4)
t
CW
(See Note 2)
t
CW
(See Note 2)
t
WP
(See Note 5)
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