參數(shù)資料
型號: AM42DL6404G
英文描述: 64 Mbit (8 M x 8-Bit/4 M x 16-Bit) CMOS and 4 Mbit (256 K x 16-Bit) Static RAM (Preliminary)
中文描述: 64兆位(8米× 8位/ 4米× 16位)CMOS和4兆位(256畝× 16位),靜態(tài)存儲器(初步)
文件頁數(shù): 50/60頁
文件大小: 956K
代理商: AM42DL6404G
March 4, 2002
Am42DL16x2D
49
P R E L I M I N A R Y
AC CHARACTERISTICS
Alternate CE#f Controlled Erase and Program Operations
Notes:
1. Not 100% tested.
2. See the “Flash Erase And Programming Performance” section for more information.
Parameter
Speed Options
JEDEC
Std
Description
70
85
Unit
t
AVAV
t
WC
Write Cycle Time (Note 1)
Min
70
85
ns
t
AVWL
t
AS
Address Setup Time (WE# to Address)
Min
0
ns
t
ASO
Address Setup Time to CE#f Low During Toggle
Bit Polling
Min
15
ns
t
ELAX
t
AH
Address Hold Time
Min
45
ns
t
AHT
Address Hold time from CE#f or OE# High During
Toggle Bit Polling
Min
0
ns
t
DVEH
t
DS
Data Setup Time
Min
35
ns
t
EHDX
t
DH
Data Hold Time
Min
0
ns
t
GHEL
t
GHEL
Read Recovery Time Before Write
(OE# High to WE# Low)
Min
0
ns
t
WLEL
t
WS
WE# Setup Time
Min
0
ns
t
EHWH
t
WH
WE# Hold Time
Min
0
ns
t
ELEH
t
CP
CE#f Pulse Width
Min
30
35
ns
t
EHEL
t
CPH
CE#f Pulse Width High
Min
30
35
ns
t
WHWH1
t
WHWH1
Programming Operation (Note 2)
Typ
7
μs
t
WHWH1
t
WHWH1
Accelerated Programming Operation (Note 2)
Typ
4
μs
t
WHWH2
t
WHWH2
Sector Erase Operation (Note 2)
Typ
0.7
sec
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