參數(shù)資料
型號: AM42DL6404G
英文描述: 64 Mbit (8 M x 8-Bit/4 M x 16-Bit) CMOS and 4 Mbit (256 K x 16-Bit) Static RAM (Preliminary)
中文描述: 64兆位(8米× 8位/ 4米× 16位)CMOS和4兆位(256畝× 16位),靜態(tài)存儲器(初步)
文件頁數(shù): 53/60頁
文件大?。?/td> 956K
代理商: AM42DL6404G
52
Am42DL16x2D
March 4, 2002
P R E L I M I N A R Y
AC CHARACTERISTICS
Figure 29.
SRAM Read Cycle
Notes:
1. WE# = V
IH
, if CIOs is low, ignore UB#s/LB#s timing.
1. t
HZ
and t
OHZ
are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output
voltage levels.
2. At any given temperature and voltage condition, t
HZ
(Max.) is less than t
LZ
(Min.) both for a given device and from device to device
interconnection.
Data Valid
High-Z
t
RC
CE#1s
Address
OE#
Data Out
t
OH
t
AA
t
CO1
t
OE
t
OLZ
t
BLZ
t
LZ
t
OHZ
t
HZ
CE2s
t
CO2
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