參數(shù)資料
型號： AM42DL6404G
英文描述： 64 Mbit (8 M x 8-Bit/4 M x 16-Bit) CMOS and 4 Mbit (256 K x 16-Bit) Static RAM (Preliminary)
中文描述： 64兆位（8米× 8位/ 4米× 16位）CMOS和4兆位（256畝× 16位），靜態(tài)存儲器（初步）
文件頁數(shù)： 40/60頁
文件大小： 956K
代理商： AM42DL6404G
March 4, 2002
Am42DL16x2D
39
P R E L I M I N A R Y
AC CHARACTERISTICS
Flash Read-Only Operations
Notes:
1. Not 100% tested.
2. See Figure 11 and Table 17 for test specifications.
Parameter
Description
Test Setup
Speed Options
Unit
JEDEC
Std
70
85
t
AVAV
t
RC
Read Cycle Time (Note 1)
Min
70
85
ns
t
AVQV
t
ACC
Address to Output Delay
CE#f, OE# = V
IL
Max
70
85
ns
t
ELQV
t
CE
Chip Enable to Output Delay
OE# = V
IL
Max
70
85
ns
t
GLQV
t
OE
Output Enable to Output Delay
Max
30
35
ns
t
EHQZ
t
DF
Chip Enable to Output High Z (Note 1)
Max
16
ns
t
GHQZ
t
DF
Output Enable to Output High Z (Note 1)
Max
16
ns
t
AXQX
t
OH
Output Hold Time From Addresses, CE#f or
OE#, Whichever Occurs First
Min
0
ns
t
OEH
Output Enable Hold
Time (Note 1)
Read
Min
0
ns
Toggle and
Data# Polling
Min
10
ns
t
OH
t
CE
Outputs
WE#
Addresses
CE#f
OE#
HIGH Z
Output Valid
HIGH Z
Addresses Stable
t
ACC
t
RC
t
OEH
t
RH
t
OE
t
RH
0 V
RY/BY#
RESET#
t
DF
Figure 14.
Read Operation Timings
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