參數(shù)資料
型號(hào): AM42DL6404G
英文描述: 64 Mbit (8 M x 8-Bit/4 M x 16-Bit) CMOS and 4 Mbit (256 K x 16-Bit) Static RAM (Preliminary)
中文描述: 64兆位(8米× 8位/ 4米× 16位)CMOS和4兆位(256畝× 16位),靜態(tài)存儲(chǔ)器(初步)
文件頁(yè)數(shù): 46/60頁(yè)
文件大?。?/td> 956K
代理商: AM42DL6404G
March 4, 2002
Am42DL16x2D
45
P R E L I M I N A R Y
AC CHARACTERISTICS
OE#
WE#
Addresses
t
OH
Data
Valid
In
Valid
In
Valid PA
Valid RA
t
WC
t
WPH
t
AH
t
WP
t
DS
t
DH
t
RC
t
CE
Valid
Out
t
OE
t
ACC
t
OEH
t
GHWL
t
DF
Valid
In
CE#f Controlled Write Cycles
WE# Controlled Write Cycle
Valid PA
Valid PA
t
CP
t
CPH
t
WC
t
WC
Read Cycle
t
SR/W
CE#f
Figure 21.
Back-to-back Read/Write Cycle Timings
WE#
CE#f
OE#
High Z
t
OE
High Z
DQ7
DQ6–DQ0
RY/BY#
t
BUSY
Complement
True
Addresses
VA
t
OEH
t
CE
t
CH
t
OH
t
DF
VA
VA
Status Data
Complement
Status Data
True
Valid Data
Valid Data
t
ACC
t
RC
Note:
VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data
read cycle.
Figure 22.
Data# Polling Timings (During Embedded Algorithms)
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