參數(shù)資料
型號(hào): AK4665AEN
元件分類: 消費(fèi)家電
英文描述: SPECIALTY CONSUMER CIRCUIT, QCC32
封裝: 5 X 5 MM, 0.50 MM PITCH, LEAD FREE, QFN-32
文件頁數(shù): 46/52頁
文件大?。?/td> 522K
代理商: AK4665AEN
ASAHI KASEI
[AK4665A]
MS0440-E-01
2006/05
- 50 -
1.
Grounding and Power Supply Decoupling
The AK4665A requires careful attention to power supply and grounding arrangements. AVDD is usually supplied from
the analog power supply in the system and DVDD&TVDD is supplied from AVDD via a 10
resistor. Alternatively if
AVDD, DVDD, TVDD and HVDD are supplied separately, the power up sequence is not critical. AVSS, DVSS and
HVSS must be connected to the analog ground plane. System analog ground and digital ground should be connected
together near to where the supplies are brought onto the printed circuit board. Decoupling capacitors should be as close to
the AK4665A as possible, with the small value ceramic capacitors being the nearest.
2. Internal Voltage Reference
Internal voltage reference is output on the VREF pin (typ. 2.1V). An electrolytic capacitor 4.7
F in parallel with a 0.1F
ceramic capacitor is attached between VREF and AVSS to eliminate the effects of high frequency noise. VCOM is
1.2V(typ) and is a signal ground of this chip. A 2.2
F electrolytic capacitor in parallel with a 0.1F ceramic capacitor
should be connected between VCOM and AVSS to eliminate the effects of high frequency noise. A ceramic capacitor
should be connected to VCOM pin and located as close as possible to the AK4665A. No load current may be drawn from
VREF and VCOM pins. All signals, especially clocks, should be kept away from the VCOM and VREF pins in order to
avoid unwanted coupling into the AK4665A.
3. Analog Inputs
The analog inputs are single-ended and the input resistance 60k
(typ) for AINL1/AINR1 pins and 60k
(typ)@0dB/
6dB or 30k (typ)@+6dB/+30dB for MICIN pin. The input signal range is 1.5Vpp (typ) centered on
VCOM voltage. Usually, the input signal cuts DC with a capacitor. The cut-off frequency is fc=(1/2
πRC). The AK4665A
can accept input voltages from AVSS to AVDD. The ADC output data format is 2’s complement. The ADC’s DC offset
is removed by the internal HPF (fc=3.4Hz@fs=44.1kHz).
4. Analog Outputs
The analog outputs are single-ended outputs. The output signal range of lineout is 1.5Vpp(typ) centered on the VCOM
voltage. The output signal range of headphone is 1.5Vpp(typ)@HPG bit = “0” or 2.83Vpp(typ)@HPG bit = “1” centered
on AVSS voltage. The input data format is 2’s compliment. The output voltage is a positive full scale for
7FFFFH(@20bit) and negative full scale for 80000H(@20bit). The ideal output is VCOM voltage (lineout) or AVSS
voltage (headphone) for 00000H(@20bit).
DC offsets on the lineout outputs is eliminated by AC coupling since the lineout outputs have a DC offset equal to VCOM
plus a few mV.
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