ASAHI KASEI
[AK4665A]
MS0440-E-01
2006/05
- 4 -
PIN/FUNCTION
No.
Pin Name
I/O
Function
1
LRCK
I
L/R Clock Pin
This clock determines which audio channel is currently being output on SDTO pin and
input on SDTI pin.
2
MCLK
I
Master Clock Input Pin
3
BICK
I
Serial Bit Clock Pin
This clock is used to latch audio data.
4
SDTI
I
Audio Data Input Pin
5
SDTO
O
Audio Data Output Pin
SDTO pin goes to DVSS when PDN pin is “L” or PMADC bit is “0”.
6
TVDD
-
Digital I/O Power Supply Pin
7
DVSS
-
Digital Ground Pin
8
DVDD
-
Digital Power Supply Pin
9
CP
O
Positive Charge Pump Capacitor Terminal Pin
10
CN
I
Negative Charge Pump Capacitor Terminal Pin
11
HVDD
-
Power Supply Pin for Headphone Amplifier and Charge Pump Circuit
12
HVSS
-
Ground Pin for Headphone Amplifier and Charge Pump Circuit
13
NVSS
O
Negative Voltage Output Pin for Headphone Amplifier and Charge Pump Circuit
14
HPL
O
Lch Headphone Amplifier Output Pin
HPL pin goes to AVSS when PMHPL bit is “0”.
15
HPR
O
Rch Headphone Amplifier Output Pin
HPR pin goes to AVSS when PMHPR bit is “0”.
16
ROUT
O
Rch Analog Output Pin
17
LOUT
O
Lch Analog Output Pin
18
MIN
I
Mono Analog Input Pin
19
RIN
I
Rch Analog Input Pin
20
LIN
I
Lch Analog Input Pin
21
AINR1
I
Rch Analog Input 1 Pin for ADC (LINE Input)
22
AINL1
I
Lch Analog Input 1 Pin for ADC (LINE Input)
23
MPWR
O
MIC Power Supply Pin
24
MICIN
I
MIC Input Pin
25
AVSS
-
Analog Ground Pin
26
AVDD
-
Analog Power Supply Pin
27
VCOM
O
Common Voltage Output Pin, 1.2V (typ, respect to AVSS)
Normally connected to AVSS pin with a 0.1
F ceramic capacitor in parallel with a
2.2
F electrolytic capacitor. VCOM pin goes to AVSS when PMVCM bit = ”0”.
28
VREF
O
Reference Voltage Output Pin, 2.1V (typ, respect to AVSS)
Normally connected to AVSS pin with a 0.1
F ceramic capacitor in parallel with a
4.7
F electrolytic capacitor. VREF pin goes to AVSS when PMVCM bit = ”0”.
29
PDN
I
Power-down Pin
When “L”, the AK4665A is in power-down mode and is held in reset. The AK4665A
should always be reset upon power-up.
30
CSN
I
Control Data Chip Select Pin
31
CCLK
I
Control Clock Input Pin
32
CDTI
I
Control Data Input Pin
Note 1. Do not allow digital input pins except analog input pins (MICIN, AINL1, AINR1, LIN, RIN and MIN pins) to
float.