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參數(shù)資料
| 型號(hào)： | AK4665AEN |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, QCC32 |
| 封裝： | 5 X 5 MM, 0.50 MM PITCH, LEAD FREE, QFN-32 |
| 文件頁數(shù)： | 32/52頁 |
| 文件大?。?/td> | 522K |
| 代理商： | AK4665AEN |
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ASAHI KASEI
[AK4665A]
MS0440-E-01
2006/05
- 38 -
4) DAC
→ Line Out
Power Supply
PDN pin
PMVCM bit
Clock Input
(4)
SDTI pin
PMDAC bit
DAC Internal
State
PD(Power-down)
Normal Operation
PMLO bit
ATTL/R7-0 bit
00H(MUTE)
FFH(0dB)
LOUT/ROUT pins
(5)
LMUTE,
ATTS3-0 bits
10H(MUTE)
0FH(0dB)
(6) GD
(7) 1061/fs
(Hi-Z)
PD
00H(MUTE)
(Hi-Z)
(5)
(6)
(7)
Don’t care
DACL,
DACR bits
(1) >150ns
(2)
>0
(3) >0
Don’t care
10H
Figure 24. Power-up/down Sequence of DAC and Line Out
(1) PDN pin should be set to “H” at least 150ns after the power is supplied.
(2) DACL and DACR bits should be changed to “1” after PDN pin goes to “H”. Each path is switched-on during the
transition time set by FS3-0 and PTS1-0 bits.
(3) PMDAC and PMLO bits should be changed to “1” after DACL and DACR pins are changed to “1”.
(4) External clocks (MCLK, BICK and LRCK) are needed to operate DAC. External clocks are also needed for each
path (DACL, LINL, MINL, DACR, RINR and MINR bits) setting.
(5) When PMLO bit is changed to “1”, pop noise is output from LOUT/ROUT pins.
(6) Digital output corresponding to analog input has the group delay (GD) of 17.5/fs (=397s@fs=44.1kHz).
(7) The transition time for digital volume is set by ATS bit. The initial value is 1061/fs (=24ms@fs=44.1kHz).
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