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參數(shù)資料
| 型號(hào)： | ADV7330 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Multiformat 11-Bit Triple DAC Video Encoder |
| 中文描述： | 多格式11位DAC的視頻編碼器三 |
| 文件頁(yè)數(shù)： | 30/76頁(yè) |
| 文件大?。?/td> | 1378K |
| 代理商： | ADV7330 |
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REV. B
–30–
ADV7330
Table IV. Async Timing Mode Truth Table
Reference in
Figures 20a and 20b
HSYNC_I/P
VSYNC_I/P
BLANK_I/P
*
1
→
0
0
0
→
1
1
1
0
0
→
1
0 or 1
0 or 1
0 or 1
0 or 1
0 or 1
0
0
→
1
1
→
0
50% point of falling edge of tri-level horizontal sync signal
25% point of rising edge of tri-level horizontal sync signal
50% point of falling edge of tri-level horizontal sync signal
50% start of active video
50% end of active video
a
b
c
d
e
*
When async timing mode is enabled,
BLANK_I/P
(Pin 25) becomes an active high input.
BLANK_I/P
is set to active low at Address 10h, Bit 6.
HD Timing Reset
[Address 14h, Bit 0]
A timing reset is achieved in setting the HD timing reset control
bit at Address 14h from 0 to 1. In this state, the horizontal and
vertical counters will remain reset. When this bit is set back to
0, the internal counters will commence counting again. PLL must
be powered off by this mode.
The minimum time the pin has to be held high is one clock cycle,
otherwise this reset signal might not be recognized. This timing
reset applies to the HD timing counters only.
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