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參數(shù)資料
| 型號： | ADV7330 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Multiformat 11-Bit Triple DAC Video Encoder |
| 中文描述： | 多格式11位DAC的視頻編碼器三 |
| 文件頁數(shù)： | 22/76頁 |
| 文件大?。?/td> | 1378K |
| 代理商： | ADV7330 |
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REV. B
–22–
ADV7330
SR7–
SR0
44h
Register
Bit Description
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting
Reset
Values
00h
SD Mode Register 3
SD VSYNC-3H
0
1
Disabled
VSYNC
= 2.5 Lines (PAL)
VSYNC
= 3 Lines (NTSC)
Genlock Disabled
Subcarrier Reset
Timing Reset
RTC Enabled
720 Pixels
710 (NTSC)/702 (PAL)
Chroma Enabled
Chroma Disabled
Enabled
Disabled
Disabled
Enabled
DAC B = Luma
DAC C = Chroma
DAC B = Chroma
DAC C = Luma
SD RTC/TR/SCR
*
0
0
1
1
0
1
0
1
SD Active Video Length
0
1
SD Chroma
0
1
SD Burst
0
1
SD Color Bars
0
1
SD DAC Swap
0
1
45h
46h
47h
Reserved
Reserved
SD Mode Register 4
00h
00h
00h
SD PrPb Scale
0
1
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
0 must be written to this bit.
0 must be written to this bit.
0 must be written to this bit.
0 must be written to this bit.
0 must be written to this bit.
Disabled
Enabled
8-Bit Input
16-Bit Input
0 must be written to this bit.
Disabled
Enabled
Disabled
Enabled
Gamma Curve A
Gamma Curve B
Disabled
–11 IRE
–6 IRE
–1.5 IRE
0 must be written to this bit.
Disabled
Enabled
Disabled
4 Clk Cycles
8 Clk Cycles
Reserved
0 must be written to this bit.
0 must be written to this bit.
SD Y Scale
0
1
SD Hue Adjust
0
1
SD Brightness
0
1
SD Luma SSAF Gain
0
1
Reserved
Reserved
Reserved
Reserved
Reserved
SD Double Buffering
0
0
0
48h
SD Mode Register 5
0
0
0
1
SD Input Format
0
1
Reserved
SD Digital Noise Reduction
0
0
1
SD Gamma Control
0
1
SD Gamma Curve
0
1
49h
SD Mode Register 6
SD Undershoot Limiter
0
0
1
1
0
1
0
1
00h
Reserved
SD Black Burst Output on DAC Luma
0
0
1
SD Chroma Delay
0
0
1
1
0
1
0
1
Reserved
Reserved
0
0
*
See Figure 23, RTC Timing and Connections.
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