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參數(shù)資料
| 型號(hào)： | ADV7330 |
| 廠(chǎng)商： | Analog Devices, Inc. |
| 英文描述： | Multiformat 11-Bit Triple DAC Video Encoder |
| 中文描述： | 多格式11位DAC的視頻編碼器三 |
| 文件頁(yè)數(shù)： | 18/76頁(yè) |
| 文件大?。?/td> | 1378K |
| 代理商： | ADV7330 |
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REV. B
–18–
ADV7330
NOTES
1
When set to 0, the line and field counters automatically wrap around at the end of the field/frame of the standard selected. When set to 1, the field/line counters are
free running and wrap around when external sync signals indicate so.
SR7–
SR0
12h
Register
Bit Description
Bit
7
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
0
0
0
0
1
Bit
1
0
0
1
1
0
Bit
0
0
1
0
1
0
Register Setting
Reset
Values
00h
HD Mode Register 3
0 Clk Cycle
1 Clk Cycle
2 Clk Cycles
3 Clk Cycles
4 Clk Cycles
0 Clk Cycle
1 Clk Cycle
2 Clk Cycles
3 Clk Cycles
4 Clk Cycles
Disabled
Enabled
Disabled
Enabled
Cb after Falling Edge of
HSYNC
Cr after Falling Edge of
HSYNC
0 must be written to this bit.
0 must be written to this bit.
Disabled
Enabled
0 must be written to this bit.
Disabled
Enabled
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
HD CGMS
0
1
HD CGMS CRC
0
1
13h
HD Mode Register 4
HD Cr/Cb Sequence
0
4Ch
1
Reserved
Reserved
Sinc Filter on DAC A, B, C
0
0
0
1
Reserved
HD Chroma SSAF
0
0
1
Reserved
HD Double Buffering
1
0
1
Disabled
Enabled
A low-high-low transition resets the
internal HD timing counters.
30 Hz/2200 Total Samples/Line
25 Hz/2640 Total Samples/Line
0 must be written to these bits.
Field Input
14h
HD Mode Register 5
HD Timing Reset
x
00h
0
0
0
1
Reserved
HD Vsync/Field Input
0
0
0
0
1
Vsync Input
Lines/Frame
1
0
Update Field/Line Counter
Field/Line Counter Free Running
1
15h
HD Mode Register 6
Reserved
HD RGB Input
0
0 must be written to this bit.
Disabled
Enabled
Disabled
Enabled
DAC E = Pr; DAC F = Pb
DAC E = Pb; DAC F = Pr
Gamma Curve A
Gamma Curve B
Disabled
Enabled
Mode A
Mode B
Disabled
Enabled
00h
0
1
HD Sync on PrPb
0
1
HD Color DAC Swap
0
1
HD Gamma Curve A/B
0
1
HD Gamma Curve Enable
0
1
HD Adaptive Filter Mode
0
1
HD Adaptive Filter Enable
0
1
HD Y Delay with respect to falling
edge of HSYNC
HD Color Delay with respect to
falling edge of HSYNC
1080i Frame Rate
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ADV7330KST | Multiformat 11-Bit Triple DAC Video Encoder |
| ADXL321 | Small and Thin 18 g Accelerometer |
| ADXL321EB | Small and Thin 18 g Accelerometer |
| ADXL321JCP | Small and Thin 18 g Accelerometer |
| ADXL321JCP-REEL | Small and Thin 18 g Accelerometer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADV73305502 | 制造商:LG Corporation 功能描述:FRAME ASSEMBLY |
| ADV73306701 | 制造商:LG Corporation 功能描述:Frame Assembly |
| ADV73306702 | 制造商:LG Corporation 功能描述:Frame Assembly |
| ADV73306703 | 制造商:LG Corporation 功能描述:Frame Assembly |
| ADV73306704 | 制造商:LG Corporation 功能描述:Frame Assembly |
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