參數(shù)資料
型號: ADV7173KSTZ-REEL
廠商: Analog Devices Inc
文件頁數(shù): 29/60頁
文件大?。?/td> 0K
描述: IC DAC VIDEO NTSC 6-CH 48LQFP
標(biāo)準(zhǔn)包裝: 2,000
類型: 視頻編碼器
應(yīng)用: 多媒體
電壓 - 電源,模擬: 4.75 V ~ 5.25 V
安裝類型: 表面貼裝
封裝/外殼: 48-LQFP
供應(yīng)商設(shè)備封裝: 48-LQFP(7x7)
包裝: 帶卷 (TR)
REV. B
ADV7172/ADV7173
–35–
TIMING REGISTER 1 (TR17–TR10)
(Address (SR4–SR0) = 0BH)
Timing Register 1 is an 8-bit-wide register.
Figure 53 shows the various operations under the control of
Timing Register 1. This register can be read from as well writ-
ten to. This register can be used to adjust the width and position
of the master mode timing signals.
TR1 BIT DESCRIPTION
HSYNC Width (TR11–TR10)
These bits adjust the
HSYNC pulsewidth.
HSYNC to FIELD/VSYNC Delay (TR13–TR12)
These bits adjust the position of the
HSYNC output relative to
the FIELD/
VSYNC output.
HSYNC to FIELD Rising Edge Delay (TR15–TR14)
When the ADV7172/ADV7173 is in Timing Mode 1, these bits
adjust the position of the
HSYNC output relative to the FIELD
output rising edge.
VSYNC Width (TR15–TR14)
When the ADV7172/ADV7173 is configured in Timing Mode
2, these bits adjust the
VSYNC pulsewidth.
HSYNC to Pixel Data Adjust (TR17–TR16)
This enables the
HSYNC to be adjusted with respect to the pixel
data. This allows the Cr and Cb components to be swapped. This
adjustment is available in both master and slave timing modes.
TR11
TR10
TR17
TR12
TR13
TR15
TR16
TR14
HSYNC TO PIXEL
DATA ADJUST
TR17 TR16
00
0
TPCLK
01
1
TPCLK
10
2
TPCLK
11
3
TPCLK
HSYNC TO
FIELD/
VSYNC DELAY
TR13 TR12
00
0
TPCLK
01
4
TPCLK
10
8
TPCLK
1
16
TPCLK
TB
HSYNC WIDTH
00
1
TPCLK
01
4
TPCLK
1
0
16
TPCLK
1
128
TPCLK
TR11 TR10
TA
HSYNC TO FIELD
RISING EDGE DELAY
(MODE 1 ONLY)
x0
TB
x1
TB + 32 s
TR15 TR14
TC
VSYNC WIDTH
(MODE 2 ONLY)
00
1
TPCLK
01
4
TPCLK
1
0
16
TPCLK
1
128
TPCLK
LINE 313
LINE 314
LINE 1
TB
TIMING MODE 1 (MASTER/PAL)
HSYNC
FIELD/
VSYNC
TA
TC
TR15 TR14
Figure 53. Timing Register 1
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