參數(shù)資料
型號： ADV7173KSTZ-REEL
廠商： Analog Devices Inc
文件頁數(shù)： 26/60頁
文件大小： 0K
描述： IC DAC VIDEO NTSC 6-CH 48LQFP
標(biāo)準(zhǔn)包裝： 2,000
類型： 視頻編碼器
應(yīng)用： 多媒體
電壓 - 電源，模擬： 4.75 V ~ 5.25 V
安裝類型： 表面貼裝
封裝/外殼： 48-LQFP
供應(yīng)商設(shè)備封裝： 48-LQFP（7x7）
包裝： 帶卷 (TR)
REV. B
ADV7172/ADV7173
–32–
MODE REGISTER 6 MR6 (MR67–MR60)
(Address (SR4–SR0) = 06H)
Mode Register 6 is an 8-bit-wide register. Figure 50 shows the
various operations under the control of Mode Register 6.
MR6 BIT DESCRIPTION
Power-Up Sleep Mode Control (MR60)
After reset this bit is set to “0,” if both SCRESET/RTC and
NTSC_PAL pins are tied high, the part will power-up in sleep
mode (to facilitate low power consumption before the I
2C is
initialized). When this bit is set to “1” (via the I
2C), sleep mode
control passes to Mode Register 2, Bit 7.
Reserved (MR61)
A Logic “0” must be written to this bit.
Luma Autodetect Control (MR62)
This bit controls which mode of autodetect operation is being
used on the luma DAC (DAC B) on the ADV7172/ADV7173.
If this bit is set (“0”), Mode 0 is on; if this bit is set (“1”), then
Mode 1 is being used.
Composite Autodetect Control (MR63)
This bit controls which mode of autodetect operation is being
used on the composite DAC (DAC A) on the ADV7172/
ADV7173. If this bit is set (“0”), Mode 0 is on; if this bit is set
(“1”), then Mode 1 is being used.
DAC Termination Control (MR64)
This bit controls the load termination resistance detected by the
autodetect functionality. If this bit is set (“0”), the autodetect
feature is used to determine if a 75
termination is present. If
this bit is set to (“1”), the autodetect feature is used to indicate
if a 150
termination is present.
Reserved (MR65)
A Logic “0” must be written to this bit.
Luma DAC Status Bit (MR66)
This bit is a read-only status bit for the autodetect feature of
the ADV7172/ADV7173 and may be read to check whether
or not the composite DAC is terminated. If this bit is set (“1”),
there is no termination; if this bit is set (“0”), the composite DAC
is terminated.
Composite DAC Status Bit (MR67)
This bit is a read only status bit for the autodetect feature of the
ADV7172/ADV7173 and may be read to check whether or not
the luma DAC is terminated. If this bit is set (“1”), there is no
termination. If this bit is set (“0”), the luma DAC is terminated.
MR61
MR60
MR67
MR62
MR64
MR63
MR65
MR66
COMPOSITE
DAC STATUS BIT
0
NOT TERMINATED
1
TERMINATED
MR67
DAC TERMINATION
CONTROL
01
MODE
12
MODE
MR64
LUMA DAC
STATUS BIT
0
NOT TERMINATED
1
TERMINATED
MR66
COMP AUTODETECT
CONTROL
0
MODE 0
1
MODE 1
MR63
LUMA AUTODETECT
CONTROL
0
MODE 0
1
MODE 1
MR62
MR61
ZERO SHOULD
BE WRITTEN TO
THIS BIT
POWER-UP SLEEP
MODE CONTROL
0
ENABLE
1
DISABLE
MR60
ZERO SHOULD
BE WRITTEN TO
THIS BIT
MR65
Figure 50. Mode Register 6 (MR6)
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