參數(shù)資料
型號(hào)： ADV7173KSTZ-REEL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 28/60頁(yè)
文件大小： 0K
描述： IC DAC VIDEO NTSC 6-CH 48LQFP
標(biāo)準(zhǔn)包裝： 2,000
類型： 視頻編碼器
應(yīng)用： 多媒體
電壓 - 電源，模擬： 4.75 V ~ 5.25 V
安裝類型： 表面貼裝
封裝/外殼： 48-LQFP
供應(yīng)商設(shè)備封裝： 48-LQFP（7x7）
包裝： 帶卷 (TR)
REV. B
ADV7172/ADV7173
–34–
TIMING REGISTER 0 (TR07–TR00)
(Address (SR4–SR0) = 0AH)
Figure 52 shows the various operations under the control of
Timing Register 0. This register can be read from as well as
written to.
TR0 BIT DESCRIPTION
Master/Slave Control (TR00)
This bit controls whether the ADV7172/ADV7173 is in master
or slave mode.
Timing Mode Selection (TR02–TR01)
These bits control the timing mode of the ADV7172/ADV7173.
These modes are described in more detail in the Timing and
Control section of the data sheet.
BLANK Input Control (TR03)
This bit controls whether the
BLANK input is used when the
part is in slave mode or whether
BLANK is internally generated.
Luma Delay (TR05–TR04)
These bits control the addition of a delay to the luminance with
respect to the chrominance. Each bit represents a delay of 74 ns.
Min Luma Value (TR06)
The bit is used to control the minimum luma value output by
the ADV7172/ADV7173. When this bit is set to (“1”), the luma
is limited to 7.5 IRE below the blank level. When this bit is set
to (“0”), the luma value can be as low as the sync bottom level.
Timing Register Reset (TR07)
Toggling TR07 from low to high and low again resets the inter-
nal timing counters. This bit should be toggled after power-up,
reset or changed to a new timing mode.
TR01
TR00
TR07
TR02
TR03
TR05
TR06
TR04
TIMING
REGISTER RESET
TR07
BLANK INPUT
CONTROL
0
ENABLE
1
DISABLE
TR03
MASTER/SLAVE
CONTROL
0
SLAVE TIMING
1
MASTER TIMING
TR00
LUMA DELAY
0
0ns DELAY
0
1
74ns DELAY
1
0
148ns DELAY
1
222ns DELAY
TR05 TR04
TIMING MODE
SELECTION
0
MODE 0
0
1
MODE 1
1
0
MODE 2
1
MODE 3
TR02 TR01
MIN LUMA VALUE
0
LUMA MIN =
SYNC BOTTOM
1
LUMA MIN =
BLANK –7.5 IRE
TR06
Figure 52. Timing Register 0
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