參數(shù)資料
型號(hào)： ADV7173KSTZ-REEL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 14/60頁(yè)
文件大?。?/td> 0K
描述： IC DAC VIDEO NTSC 6-CH 48LQFP
標(biāo)準(zhǔn)包裝： 2,000
類型： 視頻編碼器
應(yīng)用： 多媒體
電壓 - 電源，模擬： 4.75 V ~ 5.25 V
安裝類型： 表面貼裝
封裝/外殼： 48-LQFP
供應(yīng)商設(shè)備封裝： 48-LQFP（7x7）
包裝： 帶卷 (TR)
REV. B
ADV7172/ADV7173
–21–
Mode 2: Master Option
HSYNC, VSYNC, BLANK
(Timing Register 0 TR0 = X X X X X 1 0 1)
In this mode the ADV7172/ADV7173 can generate horizontal and vertical SYNC signals. A coincident low transition of both
HSYNC and VSYNC inputs indicates the start of an odd field. A VSYNC low transition when HSYNC is high indicates the start of
an even field. The
BLANK signal is optional. When the BLANK input is disabled, the ADV7172/ADV7173 automatically blanks all
normally blank lines as per CCIR-624. Mode 2 is illustrated in Figure 30 (NTSC) and Figure 31 (PAL). Figure 32 illustrates the
HSYNC, BLANK, and VSYNC for an even-to-odd field transition relative to the pixel data. Figure 33 illustrates the HSYNC,
BLANK, and VSYNC for an odd-to-even field transition relative to the pixel data.
PAL = 12 * CLOCK/2
NTSC = 16 * CLOCK/2
HSYNC
VSYNC
BLANK
PIXEL
DATA
PAL = 132 * CLOCK/2
NTSC = 122 * CLOCK/2
Cb
Y
Cr
Y
Figure 32. Timing Mode 2 Even-to-Odd Field Transition Master/Slave
PAL = 864 * CLOCK/2
NTSC = 858 * CLOCK/2
PAL = 132 * CLOCK/2
NTSC = 122 * CLOCK/2
HSYNC
VSYNC
BLANK
PIXEL
DATA
PAL = 12 * CLOCK/2
NTSC = 16 * CLOCK/2
Cb
Y
Cr
Y
Cb
Figure 33. Timing Mode 2 Odd-to-Even Field Transition Master/Slave
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