參數(shù)資料
型號： ADV212BBCZRL-150
廠商： ANALOG DEVICES INC
元件分類： 消費家電
英文描述： JPEG 2000 Video Codec
中文描述： SPECIALTY CONSUMER CIRCUIT, PBGA144
封裝： 13 X 13 MM, LEAD FREE, MO-192AAD-1, CSPBGA-144
文件頁數(shù)： 8/44頁
文件大?。?/td> 374K
代理商： ADV212BBCZRL-150
ADV212
DREQ/DACK DMA MODE—SINGLE FIFO WRITE OPERATION
Rev. 0 | Page 8 of 44
Table 6.
Parameter
DREQ Pulse Width
DACK Assert to Subsequent DREQ Delay
Mnemonic
DREQ
PULSE
t
DREQ
t
WESU
t
SU
t
HD
DACK
LO
DACK
HI
t
WEHD
WFSRQ
t
DREQRTN
Min
1 JCLK
1
2.5 JCLK
Typ
Max
15 JCLK
3.5 × JCLK + 8.5
Unit
ns
ns
WE to DACK Setup
0
ns
Data to DACK Deassert Setup
Data to DACK Deassert Hold
DACK Assert Pulse Width
DACK Deassert Pulse Width
WE Hold After DACK Deassert
2
2
2 JCLK
2 JCLK
0
ns
ns
ns
ns
ns
WE Assert to FSRQ Deassert (FIFO Full)
DACK to DREQ Deassert (DR × PULS = 0)
1.5 JCLK
2.5 JCLK
2.5 × JCLK + 7.5
3.5 × JCLK + 9.0
ns
ns
1
For a definition of JCLK, see Figure 32.
WE
DACK
DREQ
HDATA
3
2
1
0
DREQ
PULSE
t
DREQ
DACK
HI
DACK
LO
t
WESU
t
SU
t
HD
t
WEHD
0
Figure 5. Single Write for DREQ/DACK DMA Mode for Assigned DMA Channel
(EDMOD0/EDMOD1 <14:11> Not Programmed to a Value of 0000)
WE
DACK
DREQ
HDATA
0
1
2
t
DREQRTN
DACK
HI
DACK
LO
t
WESU
t
SU
t
HD
t
WEHD
0
Figure 6. Single Write for DREQ/DACK DMA Mode for Assigned DMA Channel
(EDMOD0/EDMOD1 <14:11> Programmed to a Value of 0000)
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