參數(shù)資料
型號(hào)： ADV212BBCZRL-150
廠商： ANALOG DEVICES INC
元件分類(lèi)： 消費(fèi)家電
英文描述： JPEG 2000 Video Codec
中文描述： SPECIALTY CONSUMER CIRCUIT, PBGA144
封裝： 13 X 13 MM, LEAD FREE, MO-192AAD-1, CSPBGA-144
文件頁(yè)數(shù)： 15/44頁(yè)
文件大?。?/td> 374K
代理商： ADV212BBCZRL-150
ADV212
VDATA MODE TIMING
Rev. 0 | Page 15 of 44
Table 11.
Parameter
VCLK to VDATA Valid Delay (VDATA Output)
VDATA Setup to Rising VCLK (VDATA Input)
VDATA Hold from Rising VCLK (VDATA Input)
HSYNC Setup to Rising VCLK
HSYNC Hold from Rising VCLK
VCLK to HSYNC Valid Delay
VSYNC Setup to Rising VCLK
VSYNC Hold from Rising VCLK
VCLK to VSYNC Valid Delay
FIELD Setup to Rising VCLK
FIELD Hold from Rising VCLK
VCLK to FIELD Valid
Decode Slave Data Sync Delay
(HSYNC Low to First 0xFF of EAV/SAV Code)
Decode Slave Data Sync Delay
(HSYNC Low to First Data for HVF Mode)
1
The sync delay value varies according to the application. Refer to the
ADV212 User Guide
for more information.
Mnemonic
VDATA
TD
VDATA
SU
VDATA
HD
HSYNC
SU
HSYNC
HD
HSYNC
TD
VSYNC
SU
VSYNC
HD
VSYNC
TD
FIELD
SU
FIELD
HD
FIELD
TD
SYNC DELAY
Min
4
4
3
4
3
4
4
3
Typ
8
1
Max
12
12
12
12
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
VCLK cycles
10
1
VCLK cycles
Cr
Y
Cb
Y
FF
EAV
FF
SAV
Cb
Y
Cr
VCLK
VDATA (IN)
00
00
00
00
VDATA
SU
VDATA
HD
0
Figure 21. Encode Video Mode Timing—CCIR 656 Mode
HSYNC
HSYNC
HD
HSYNC
SU
VCLK
Cb
Y
Cb
Y
Cr
Y
VDATA (IN)
Cr
Y
0
Figure 22. Encode Video Mode Timing—HVF Mode (HSYNC Timing)
(HSYNC Programmed for Negative Polarity)
VSYNC
VSYNC
SU
VCLK
FIELD
FIELD
SU
FIELD
HD
VSYNC
HD
0
Figure 23. Encode Video Mode Timing—HVF Mode (VSYNC and FIELD Timing)
(VSYNC and FIELD Programmed for Negative Polarity)
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