參數資料
型號： ADV212BBCZRL-150
廠商： ANALOG DEVICES INC
元件分類： 消費家電
英文描述： JPEG 2000 Video Codec
中文描述： SPECIALTY CONSUMER CIRCUIT, PBGA144
封裝： 13 X 13 MM, LEAD FREE, MO-192AAD-1, CSPBGA-144
文件頁數： 26/44頁
文件大?。?/td> 374K
代理商： ADV212BBCZRL-150
ADV212
ADV212 INTERFACE
There are several possible modes to interface to the ADV212 using
the VDATA bus and the HDATA bus or the HDATA bus alone.
VIDEO INTERFACE (VDATA BUS)
The video interface can be used in applications in which
uncompressed pixel data is on a separate bus from compressed
data. For example, it is possible to use the VDATA bus to input
uncompressed video while using the HDATA bus to output the
compressed data. This interface is ideal for applications
requiring very high throughput, such as live video capture.
Optionally, the ADV212 interlaces ITU-R BT.656 resolution
video on the fly prior to wavelet processing, which yields
significantly better compression performance for temporally
coherent frame-based video sources. Additionally, high
definition digital video such as SMPTE 274M (1080i) is
supported using two or more ADV212 devices.
The video interface can support video data or still image data
input/output in 8-/10-/12-bit formats, in YCbCr format, or in
single input mode. YCbCr data must be in 4:2:2 format.
Video data can be input/output in several different modes on
the VDATA bus, as described in Table 17. In all these modes,
the pixel clock must be input on the VCLK pin.
Rev. 0 | Page 26 of 44
Table 17. Video Input/Output Modes
Mode
Description
EAV/SAV
Accepts video with embedded EAV/SAV codes, where
the YCbCr data is interleaved onto a single bus.
HVF
Accepts video data accompanied with separate H,
V, and F signals, where YCbCr data is interleaved
onto a single bus.
Raw Video Used for still picture data and nonstandard video.
VFRM, VSTRB, and VRDY are used to program the
dimensions of the image.
HOST INTERFACE (HDATA BUS)
The ADV212 can connect directly to a wide variety of host
processors and ASICs using an asynchronous SRAM-style
interface, DMA accesses, or streaming mode (JDATA) interface.
The ADV212 supports 16- and 32-bit buses for control and
8-/16-/32-bit buses for data transfer.
The control and data channel bus widths can be specified
independently, which allows the ADV212 to support
applications that require control and data buses of different
widths.
The host interface is used for configuration, control, and status
functions, as well as for transferring compressed data streams. It
can be used for uncompressed data transfers in certain modes.
The host interface can be shared by as many as three concurrent
data streams in addition to control and status communications.
The data streams are
Uncompressed tile data (for example, still image data)
Fully encoded JPEG 2000 code stream (or unpackaged
code blocks)
Code-block attributes
The ADV212 uses big endian byte alignment for 16- and 32-bit
transfers. All data is left-justified (MSB).
Pixel Input on the Host Interface
Pixel input on the host interface supports 8-/10-/12-/14-/16-bit
raw pixel data formats. It can be used for pixel (still image)
input/output or compressed video output. Because there are no
timing codes or sync signals associated with the input data on
the host interface, dimension registers and internal counters are
used and must be programmed to indicate the start and end of
the frame. Refer to the
ADV202 in HIPI Mode
technical note
for
information about using the ADV212 in this mode.
Host Bus Configuration
For maximum flexibility, the host interface provides several
configurations to meet particular system requirements. The
default bus mode uses the same pins to transfer control, status,
and data to and from the ADV212. In this mode, the ADV212
can support 16- and 32-bit control transfers and 8-/16-/32-bit
data transfers. The size of these buses can be selected
independently, allowing, for example, a 16-bit microcontroller
to configure and control the ADV212 while still providing
32-bit data transfers to an ASIC or external memory system.
DIRECT AND INDIRECT REGISTERS
To minimize pin count and cost, the number of address pins
is limited to four, which yields a total direct address space of
16 locations. These locations are most commonly used by the
external controller and are, therefore, accessible directly. All
other registers in the ADV212 can be accessed indirectly
through the IADDR and IDATA registers.
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相關代理商/技術參數
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ADV212-HD-EB 功能描述:BOARD EVALUATION FOR ADV212-HD RoHS:否 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:- 標準包裝:1 系列:PCI Express® (PCIe) 主要目的:接口，收發(fā)器，PCI Express 嵌入式:- 已用 IC / 零件:DS80PCI800 主要屬性:- 次要屬性:- 已供物品:板
ADV212XBCZ-150 制造商:Analog Devices 功能描述:JPEG2000 VIDEO CODEC - Bulk
ADV216BBCZ 制造商:Analog Devices 功能描述:- Trays
ADV226KBCZ 制造商:Analog Devices 功能描述:
ADV226KBCZRL 制造商:Analog Devices 功能描述:
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